Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2000-10-16
2002-03-19
Zweizig, Jeffrey (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S551000, C326S066000
Reexamination Certificate
active
06359492
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention is directed to an arrangement for level conversion of high-frequency low-voltage signals that are to be transmitted between systems of different low-voltage technology fields.
2. Description of the Related Art
The transmission of high-frequency low-voltage signals is increasing in significance, whether in the transmission of data signals or in the transmission of clock signals. The low-voltage signals are generated at the emitting side within the boundary conditions and parameters of a specific technology field. Attempts have always been made to employ the same technology at the receiver side in order to avoid losses and to particularly reduce attenuations.
Applications have been identified in which changing technology fields is advantageous. In such instances, however, it is necessary to adapt the high-frequency low-voltage signals to be transmitted that have been generated within the boundary conditions and parameters of one technology system to the boundary conditions and parameters of the other technology system. This is even required when the same supply voltage conditions are employed, for instance Vcc=3.3 V to ground potential.
A typical case of a level conversion is the transmission of clock signals from a low-voltage pseudo-ECL system to a low-voltage CMOS system and vice versa.
The problem underlying the invention is explained in greater detail on the basis of
FIG. 2 and a
specific application, namely the clock supply of high bit rate switching network structures in a narrowband switching system such as EWSD with a PLL system comprising a quartz oscillator, as explained, for example, in German Patent Application No. 199 43 172.8 filed Sep. 9, 1999.
FIG. 2
shows a function unit with which the switching network clock CLK
2
at 2.048 KHz and an appertaining frame marking bit signal or, respectively, frame clock signal FMB
2
at 8 KHz supplied from a preceding function unit (not shown) is converted into the required high-frequency clock signals. This function unit contains a middle, analog or, respectively, discrete part
21
with a 184 MHz sine oscillator in an LC structure in the form of a VCO
6
. A low-voltage CMOS part
22
and a low-voltage pseudo-ECL part
23
are also provided, where the term “low-voltage” or “low-tension” is respectively indicated by the abbreviation LV.
At its input side, the low-voltage CMOS part
22
receives the clock signal CLK
2
and the frame clock signal FMB
2
. At its output side, the low-voltage pseudo-ECL part
23
outputs a high-frequency clock signal CLK
92
, preferably at 92.16 MHz, and a frame marking clock signal or, respectively, frame clock signal FMB
92
, likewise at 8 KHz, that is decoupled from the frame clock signal FMB
2
of the input side. The supplied clock signal CLK
2
is supplied to a phase detector
8
(PD) in the low-voltage CMOS part
22
, the phase detector being constructed in the form of an exclusive-OR element.
The output signal of the low-voltage CMOS part
22
enters via a low-pass filter
9
(loop filter) with a limit frequency of 200 KHz into a VCO
6
that is discretely constructed. The output signal of the VCO
6
at 184 MHz is an input signal of a comparator
73
of a converter
7
in the low-voltage pseudo-ECL part
23
. The comparator
73
compares to an internal reference signal
74
and outputs its output signal to two dividers
71
and
72
. Here, the divider
71
is a 1:2 divider that outputs a signal with the frequency 92.16 MHz at its output side as clock signal CLK
92
. The other divider
72
is a 1:6 divider that feeds back an output signal at 30.72 MHz as feedback signal via a feedback loop
13
. In the analog part
21
, the feedback loop
13
contains a level converter
14
for the conversion from the low-voltage pseudo-ECL level onto the low-voltage CMOS level and further contains a step-down device
15
in the low-voltage CMOS part
22
that is fashioned as a 1:15 divider in order to again obtain a signal with the frequency 2.048 KHz. This signal is resupplied to the phase detector
8
as a feedback signal.
The low-voltage CMOS divider
22
also contains a synchronizer
18
that receives the frame clock signal at 8 KHz at its input side and that is synchronized by the fedback signal divided down by the step-down device
15
. The output signal of the synchronizer
18
, which is already decoupled in phase position here from the phase of the frame clock signal FMB
2
of the input side, is supplied to a phase element
16
in the low-voltage pseudo-ECL part
23
via a level converter
17
in the analog part
21
for conversion from the low-voltage CMOS level onto the low-voltage pseudo-ECL level, the phase element
16
—for phase drive—receiving the output signal of the divider
72
or of an identical divider as well as the output signal of the divider
71
, i.e., the high-frequency clock signal CLK
92
, and, using these signals and two ultra-fast flip-flops in the phase element
16
, adapting the phase position of the output frame clock signal FMB
92
with 8 KHz to the output clock signal CLK
92
, first roughly and then finely.
What the division of the components onto the CMOS part
22
and the pseudo-ECL part
23
effects is that time-critical functions are realized in the low-voltage pseudo-ECL part
23
and gate-intensive functions are realized in the low-voltage CMOS part
22
. The functions in the low-voltage CMOS part
22
are thereby expediently realized with standardized, electrically programmable logic fields (FPGA), whereas the functions in the low-voltage pseudo-ECL part
23
are realized with the assistance of ultra-fast, discrete components. The connection of the interfaces of said two parts
22
and
23
occurs in the middle part
21
via exclusively analog or, respectively, passive components, as a result of which the immunity of the overall system to noise influences is enhanced. The required power supply of the individual parts
21
,
22
and
23
is expediently island-like/isolated, i.e., respectively separately implemented, in order to suppress noise infeeds among one another and from clock-alien regions of the various parts. Expediently, the level converters
14
and
17
should prevent a source for jitter or for noise emissions from arising.
The initially cited problems arise in the implementation of such an arrangement. This is especially true when each of the parts
22
and
23
is optimally designed in view of the payload signals to be processed, particularly when using commercially available components.
The module MC100LVEL38 of Motorola, a “low skew clock generation chip”, was proposed in the low-voltage pseudo-ECL part
23
in one implementation. This module is optimally suited for the conversion of high-frequency sine signals (from the VCO
6
) into the required logic level in the low-voltage pseudo-ECL part
22
. As a result of an internal 1:6 frequency divider, use in high-frequency PLL applications to far above 100 MHZ is especially beneficial since a feedback signal can be output to the low-voltage CMOS part
22
, namely its step-down device
15
, without intermediate amplifiers or dividers. This can be realized by standardized, electrically programmable logic fields FPGA that have a relatively high input capacitance of 15 through 20 pF. The phase element
16
can in turn be implemented with the module MC100LVEL51 of Motorola, an “ultra high speed differential clock D-flip flop”. As a result of its negligible gray switching area (clock/data-timing ts+th≦100 ps), this module is optimally suited for the sampling function in the phase-in in the low-voltage pseudo-ECL region
23
of the high-frequency signal.
The following technology families have been taken into consideration in the low-voltage CMOS part
22
in the realization:
ASIC
FPGA
Texas Instruments
XILINX
ALTEPA
TGC 4000
FC 4000
FLEX 6000
Technology: “sea of
LVCMOS
CMOS
gates”
I/O types
I/O types
I/O types
LVTTL_I
LVTTL_I
TTL_I
PBCL_I
LVCMOS_I
CMOS_I
LVDS_O
LVCMOS_O
CMOS_O
LVCMOS_O
Specific high-speed connections can be rea
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