Arrangement for improving defect scanner sensitivity and scannin

Details Arrangement for improving defect scanner sensitivity and scannin Arrangement for improving defect scanner sensitivity and scannin

1996-05-09

1999-06-29

Brown, Glenn W.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

438 14, 382147, 382149, 382151, G01R 31265, G06K 974

Patent

active

059173327

ABSTRACT:
Defect scanner sensitivity and accuracy are improved for light scattering defect scanners and pattern matching defect scanners by calibrating the defect scanners to each die on a wafer using preset marks on the corresponding die. The marks have a predetermined size based on the sensitivity of the defect scanners and a predetermined position relative to the circuit pattern on the corresponding die. Alignment of the defect scanners to a specific die provides improvement in coordinate accuracy over alignment with respect to an entire wafer. A layout mapping defect filtering system collects defect scan data and determines the interaction between the detected defects and a circuit layout. The layout mapping defect filtering system provides automatic identification in real time of killer defects that cause failure of the completed integrated circuit, and classifies and analyzes defects to identify potential killer defects within specified defect classes to identify defective die. The system provides accurate yield estimation to determine whether a produced wafer should be scrapped, and also provides accumulated data for yield improvement studies including quality control and circuit redesign.

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