Arrangement for generating multiple clocks in field...

Details Arrangement for generating multiple clocks in field... Arrangement for generating multiple clocks in field...

2001-05-21

2004-07-06

Miska, Vit W. (Department: 2841)

Horology: time measuring systems or devices

Electrical time base

C327S145000, C327S291000, C375S224000, C702S115000

Reexamination Certificate

active

06760277

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to testing the design of a prescribed system using field programmable gate arrays prior to implementation on mass-produced application-specific integrated circuits (ASICs).
2. Background Art
Local area networks use a network cable or other media to link stations on the network. Each local area network architecture uses a media access control (MAC) enabling network interface devices at each network node to access the network medium.
Switched local area networks such as Ethernet (IEEE 802.3) based systems are encountering increasing demands for higher speed connectivity, more flexible switching performance, and the ability to accommodate more complex network architectues. Hence, network switch designers and test engineers need to be able to minimize the time and expense needed to evaluate designs during prototyping of Ethernet-based network systems, for example an integrated multiport switch as illustrated in commonly-assigned U.S. Pat. No. 5,953,335.
Integrated network switches are implemented by reduction to silicon as an application-specific integrated circuit. Implementation of such integrated network switches using application-specific integrated circuits (ASICs) typically requires reduction to silicon of laze amounts of programming code, written for example at Register Transfer Level (RTL) using Hardware Description Language (HDL). The programming code is used to specify the operations for the network switch.
Typically field programmable ASICs, for example field program able gate arrays (FPGAs), can be used for testing the design, logic and operation of a device under test on a test board; once the design of the device under test has been fully tested and validated, the design of the device under test is converted to a mask programmable ASIC for production purposes.
One problem in testing communications designs using FPGAs, such for testing designs implementing the above-described integrated multiport switch, involves the errors introduced when multiple clock domains are required. In particular,
FIG. 1
is a diagram illustrating a conventional (Prior Art) test system
10
having oscillators
12
a
and
12
b
for generating respective clock signals (CLK
1
and CLK
2
) for use by communications devices
14
a
and
14
b
. The clock signals CLK
1
and CLK
2
are intended to be used by the communications devices
14
a
and
14
b
for sending data between each other. For example, the first clock signal CLK
1
may be used by a first logic module
18
within each of the communications devices
14
a
and
14
b
for performing internal logic operations (e.g., internal data transfer, switch processing, etc.), whereas the second clock signal CLK
2
may be used to drive a transmit and receive logic module
20
for transfer of data between the communications devices
14
a
and
14
b
at prescribed data rates.
However, the supply of the clock signals CLK
1
and CLK
2
across the clock signal paths
16
a
and
16
b
may introduce errors in that the propagation delays and/or capacitance introduced by the clock signal paths
16
a
and
16
b
may skew the clock signal timing between the clock signals. Hence, the data trier between the communications devices
14
a
and
14
b
may be out of sync depending on the relationship between the fast clock signal CLK
1
and the second clock signal CLK
2
.
SUMMARY OF THE INVENTION
There is a need for an arrangement that ensures reliable transfer of data between multiple communications devices utilizing multiple clock domains.
There also is a need for an arrangement that enables multiple communications devices to be synchronized without the necessity of multiple oscillator sources for driving respective clock domains in the communications devices.
These and other needs are attained by the present invention, where a test system for a design of a network device under test includes an oscillator configured for generating a first clock signal for a first clock domain, and field programmable gate arrays. Each field programmable gate array is configured for performing device operations according to the first clock domain and transferring data to another device at a network data rate based on a second clock domain. Each field programmable gate array includes clock conversion logic configured for generating a second clock signal for the second clock domain, based on the first clock signal. Hence, the generation of the second clock signal within each field programmable gate array ensures that timing accuracy is maintained, enabling communication between the field programmable gate arrays at high-speed data rates based on the second clock domain.
One aspect of the present invention provides a method. The method includes outputting from a clock source a first clock signal for a first clock domain to first and second devices. The first and second devices each have a first logic module configured for operating according to the first clock domain and a second logic module configured for outputting data according to a second clock domain. The method also includes generating within each of the first and second devices a second clock signal, based on the first clock signal, for the corresponding second clock domain, and transferring data between the first and second devices according to the second clock domain.
Another aspect of the present invention provides a test system. The test system includes a clock source configured for outputting a first clock signal, and first and second devices. Each of the first and second devices includes a first logic module, a converter, and a second logic module. The first logic module is configured for operating according to a first clock domain based on the first clock signal. The converter is configured for generating a second clock signal based on the first clock signal, and the second logic module is configured for transferring data to a corresponding connected device according to a second clock domain based on the second clock signal.
Additional advantages and novel features of the invention will be set forth in part in the description which follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. She advantages of the present invention may be realized and attained by means of instrumentalities and combinations particularly pointed in the appended claims.


REFERENCES:
patent: 5430397 (1995-07-01), Itoh et al.
patent: 5544203 (1996-08-01), Casanata et al.
patent: 5751665 (1998-05-01), Tanoi
patent: 5953335 (1999-09-01), Erimli et al.
patent: 6285172 (2001-09-01), Torbey
patent: 6467044 (2002-10-01), Lackey

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