Arrangement for DPCM-coding with high data rate

Details Arrangement for DPCM-coding with high data rate Arrangement for DPCM-coding with high data rate

1989-05-01

1990-01-09

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358136, H04N 712

Patent

active

048931845

ABSTRACT:
An arrangement for DPCM coding with high data rate. In a DPCM coder, wherein respective prediction values (s) are subtracted from digitized picture element signals (s), the difference signals that result represent the prediction error .DELTA. supplied to a circuit element for cutputting a quantization error (11) pertaining to a difference signal. In a following adder, quantization errors (q) are added to the prediction errors (.DELTA.), whereby the quantized prediction error (.DELTA.q) can be taken at the output of the following adder. For forming the reconstructed picture element signal (s.sub.R), the quantization error (q) is added to the current picture element signal (s) in a first adder and is supplied to a first subtraction means via a predictor. In an embodiment of the circuit, a DPCM structure that has a shortest possible critical path for a DPCM structure that is composed of a quantizer, of an addition and of a register can be produced by dividing the predictor upon insertion or removal of individual registers.

REFERENCES:
patent: 4743967 (1988-05-01), Takenaka et al.
patent: 4748503 (1988-05-01), Pirsch
"Design of a DPCM Codec for VLSI Realization in CMOS Technology", by Peter Pirsch, in IEEE, vol. 73, No. 4, Apr. 1985, pp. 592-598.
"Architektur und Schaltkreistechnik Von CMOS-ICS Fur Die DPCM-Codierung Von Videosignalen", by Peter Pirsch, Mitteilung aus dem Forschungszentrum der Standard Elektrik Lorenz AG, Stuttgart, pp. 213-222.

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