Arrangement for DPCM-coding of video signals

Details Arrangement for DPCM-coding of video signals Arrangement for DPCM-coding of video signals

1989-05-01

1990-01-02

Groody, James J.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358136, H04N 712

Patent

active

048916986

ABSTRACT:
An arrangement for DPCM-coding of video signals. A DPCM coder wherein estimated values (s) are respectively subtracted from digitized picture element signals (s) and the estimated errors are used for signal transmission after quantization and coding. Every estimated value (s) is derived from a reconstructed picture element signal formed in an adder. A limiter between the first adder and the subtractor that reduces the calculating speed can be removed from the time-critical path in that the limiter function is distributed onto two paths that calculate in parallel. A subtraction of the signal taken at the adder output occurs in the one path; the subtraction of an upper or lower limit value (.alpha..multidot.G.sup.-, .alpha..multidot.G.sup.+) weighed with .alpha. and through-connected via a switch from the respective picture element signal (s) of the input side is carried out on the other path. An overflow recognition element and a multiplexer provide that only a difference of the two differences formed up to this point, that relate to the actual addition result (no overflow, positive overflow, negative overflow), is through-connected to a quantizer.

REFERENCES:
patent: 4743967 (1988-05-01), Takenaka et al.
"Design of DOCM Codec for VLSI Realization in CMOS Technology", by Peter Pirsch, in IEEE, vol. 73, No. 4, Apr. 1985, pp. 592-598.

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