Patent
1990-07-31
1993-07-20
Eng, David Y.
G06F 1100, G06F 1324, G06F 1516
Patent
active
052300439
ABSTRACT:
An arrangement for communication between two CPUs which allows diagnosis of whether the cause of an interrupt in communication between the CPUs is due to a routine interrupt or a failure in the communication line. Timers generate overflow signals in the event that data from one or the other CPU is late in arriving. Lateness is determined by comparing the timer values to stored values in memory. Control units respond to the timers and switch the transmission level of the CPUs so that they pass a predetermined signal pattern between themselves, indicating that the interrupt is in effect but that communication lines are still open. When one of the CPUs fails to detect the confirmation signal, the CPU causes a communication failure to be indicated.
REFERENCES:
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patent: 4430700 (1984-02-01), Chadima et al.
patent: 5023778 (1991-06-01), Simon et al.
patent: 5107456 (1991-04-01), Schuur
Ichihashi Takao
Matsumoto Masashi
Yamada Syuji
Eng David Y.
Mita Industrial Co. Ltd.
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