Arrangement for detecting the binary values of bit cells having

Details Arrangement for detecting the binary values of bit cells having Arrangement for detecting the binary values of bit cells having

1978-11-29

1981-07-28

Grimm, Siegfried H.

Demodulators

Amplitude modulation demodulator

Having specific distortion, noise or other interference...

329104, 360 42, 360 29, H03K 900, G11B 506

Patent

active

042812917

ABSTRACT:
Data, in the form of a sequence of binary bits of frequency F.sub.O, is detected by deriving a clock signal H of frequency F.sub.O in response to the sequence. A level transposing device responsive to the sequence and signal H derives a bi-level signal DEI. An integrating apparatus responds to DEI to derive a signal DEINT. A decision circuit responsive to DEINT determines the polarity of signal DEINT and derives binary data bits having values that are a function of the polarity. The direction and duration of charging current supplied to a pair of capacitors of the integrator are controlled as a function of the polarity and duration of each of the levels of signal DEI, so the capacitors are respectively charged in response to even and odd numbered bits. The integrator is reset to zero at the end of the integrating operation for each level and the capacitive integrating member is supplied with a charging current proportional to F.sub.O. The voltages across the integrators are compared, by subtracting, during each bit. The polarity of the integrated difference determines the bit value, while the presence of a phase error is determined by comparing the integrated difference with a reference to derive a pair of signals indicating the polarity of the reference relative to the differences and the complement of the difference. If the difference and its complement have the same polarity relative to the reference, a phase error exists.

REFERENCES:
patent: 3699554 (1972-10-01), Jones
patent: 3789207 (1974-01-01), Jones
patent: 3818501 (1974-06-01), Fiorino
patent: 3864583 (1975-02-01), Fiorino
patent: 3877027 (1975-04-01), Marino
Ferrier, Jr. et al., "Item Identifying Asymmetrical Coding," IBM Technical isclosure Bulletin, vol. 14, No. 4, Sep. 1971, pp. 1286-1287.
J. S. Swartz, "High-Speed VFO and Data Separator," IBM Technical Disclosure Bulletin, vol. 13, No. 1, Jun. 1970, pp. 117-118.

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