Arrangement for correcting the phase of a data sampling...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input

Reexamination Certificate

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C327S231000, C327S237000

Reexamination Certificate

active

11038061

ABSTRACT:
In a clock phase corrector appropriately correcting the phase of a data sampling clock signal, a series of shift registers responds to respective sampling clock signals to store received data sequentially. The stored data are duplicated by a comparator register in response to corresponding clock signals to output a demodulated signal. A corrector shift register is provided to store sampled data in response to a clock signal. The data thus stored are then held in a reception register as intended reception data. A comparator compares the demodulated signal with the intended reception data. Based upon a result from the comparison, a bit adder produces the number of inconsistent bits. Another comparator compares the number of inconsistent bits with the number of error acceptance bits stored in an error acceptance memory to generate a phase detection signal, in response to which a timing control adjusts the phase of a data sampling clock signal.

REFERENCES:
patent: 5787132 (1998-07-01), Kishigami et al.
patent: 5920220 (1999-07-01), Takao et al.
patent: 6280774 (2001-08-01), Rang
patent: 6618459 (2003-09-01), Tada

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