Arrangement for correcting burst errors in shortened cyclical bl

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371 45, G06F 1110

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046988130

ABSTRACT:
A system for correcting burst errors with a maximum length of b bits in a reception signal, according to an error trapping method in cyclical block codes shortened by i bits, and wherein n bits are provided formed by r bits for a check part and k bits for the information. A syndrome register is provided having r stages. An overall input of the syndrome register is connected to a first exclusive-OR gate connected between two of the stages, a position of the first exclusive-OR gate being determined from coefficients of a pre-multiplication polynomial p.sub.2 (x). An output of a last stage of the syndrome register is connected via a switch to a first stage of the register and also to at least one further exclusive-OR gate connected between two stages of the register whose position is derived from a generator polynomial g(x) of the code. A zeros recognition unit is connected to each of the last r-b stages of the syndrome register. A buffer memory having n stages is provided which is connected to the overall input. A second exclusive-OR gate is connected to the output of the buffer memory, and is connected at a second input via a second switch to the output of the syndrome register. An output of the second exclusive OR gate forms an overall output of the system. An executive sequencer unit is provided for synchronizing the switches.

REFERENCES:
patent: 3542756 (1970-11-01), Gallager
patent: 3801955 (1974-04-01), Howell
patent: 4059825 (1977-11-01), Greene
patent: 4488302 (1984-12-01), Ahamed
L. R. Bahl, "Shortened Cyclic Cod with Burst Error Detection and Sync. Recovery Capability", IBM Tech., vol. 16, No. 6, 11/1973, pp. 2026-2027.
Lin, An Introduction to Error-Correcting Codes, 1970, pp. 87-91.
Error-Correcting Codes, Second Edition, W. Wesley Peterson and E. J. Weldon, Jr., The MIT Press, Cambridge, Mass. 1972, pp. 364 through 370.

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