Arrangement for checking the synchronization of a receiver

Details Arrangement for checking the synchronization of a receiver Arrangement for checking the synchronization of a receiver

1982-04-27

1984-01-31

Griffin, Robert L.

Pulse or digital communications

Spread spectrum

Direct sequence

375 94, 340347SH, H04L 706

Patent

active

044294069

ABSTRACT:
When frequency division is used as part of the clock signal regeneration process from a received data signal, a phase ambiguity may occur. A data signal receiver for a bi-phase modulated signal comprises a filter 1 feeding a sampling switch 2 which feeds a polarity detector 3 from which the decoded data is reproduced. The phase of the sampling switch 2 is controlled by the output 6-Q of a .div.2 frequency divider 6 which is driven by a phase-locked loop 5 which in turn is driven by a zero-crossing detector 4 at twice the bit frequency. A monitoring arrangement 8 has sampling switches 10 and 11 driven by outputs 6Q and 6-Q of the frequency divider 6. The data signal applied through a full-wave rectifier 9, is sampled at instants t.sub.o and t.sub.1, at twice the bit frequency. The outputs of the sample switches 10 and 11 are fed to minimum voltage detectors 12 and 13, respectively, which detect the minimum value of the samples over a number of cycles of the respective input and apply this value to the inputs of a comparator 14. If the output of detector 12 is more positive than that of detector 13, the receiver is correctly synchronized but if the output of detector 13 becomes more positive than that of the detector 12, the output of the comparator changes state and causes a pulse to be applied to input 6-1 of the divider to change the phase of the divider output 6-Q.

REFERENCES:
patent: 3846583 (1974-11-01), Boulter
patent: 4176248 (1979-11-01), Sheets
patent: 4313088 (1982-01-01), Van Gerwen et al.
patent: 4313203 (1982-01-01), Van Gerwen et al.
patent: 4317212 (1982-02-01), Van Gerwen et al.

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