Arrangement for bit-parallel addition of binary numbers with car

Details Arrangement for bit-parallel addition of binary numbers with car Arrangement for bit-parallel addition of binary numbers with car

1987-06-10

1989-12-19

Kemeny, Emanuel S.

Boots, shoes, and leggings

G06F 750

Patent

active

048887234

ABSTRACT:
A series of adders (AD.sub.i) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, in case the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by the carry bit thereof. The element AD.sub.kn-1 has the same number of transistors as the other adders AD.sub.0 . . . AD.sub.n-2.

REFERENCES:
patent: 4110832 (1987-08-01), Leininger et al.
patent: 4819198 (1989-04-01), Noll et al.
J. Jump et al., "Effective Pipelining of Digital Systems", IEEE Trans. on Computers, vol. C-27, No. 9, Sep., 1978, pp. 855-865.
K. Hwang, "Computer Arithmetic", John Wiley & Sons (1979), pp. 98-103.

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