Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Reexamination Certificate
2002-04-02
2004-07-20
Williams, Alexander Oscar (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
C257S723000, C257S685000, C257S691000, C257S712000, C257S706000, C257S207000, C257S208000, C257S291000, C257S111000, C257S106000, C257S114000, C438S125000, C438S720000, C438S122000
Reexamination Certificate
active
06765290
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates in general to electronic circuits and components therefor, such as, but not limited to those employed in subscriber line interface circuits (SLICs), and is particularly directed to a reduced complexity, diode coupling-based technique for back-biasing each of the semiconductor substrates of a plurality of integrated circuits at the maximum (most negative) DC voltage applied to any individual circuit.
BACKGROUND OF THE INVENTION
In order to optimize the performance of an integrated circuit, it is usually preferred that the semiconductor (silicon) substrate in which transistors of the circuit are formed be back-biased at the largest DC potential applied to the circuit. For the typical case of an N-conductivity type silicon substrate, this means back-biasing the substrate at the most negative DC voltage. Where the conductivity of the IC's substrate is reversed (P-type), the back-biasing voltage is the most positive DC voltage. Coupled with this requirement are continuing industry efforts to reduce circuit packaging size.
To this latter end, many of today's components are packaged using micro lead frame (MLF) technology. As illustrated in the diagrammatic side view of
FIG. 1
, a typical MLF package
10
contains an integrated circuit chip (semiconductor support structure or substrate/body)
11
, in which one or more circuits are formed, and which is mounted atop a thermally and electrically conductive (e.g., metallic) layer or pad
12
. The metallic pad
12
serves to both dissipate heat generated within the chip proper and also provides an effective means to back-bias the substrate
11
.
The MLF package also includes a plurality of circuit connection leads
13
that extend between external (e.g., surface-mount) connection pads
14
and various input/output and biasing nodes of the chip
11
. In the mounted position of the MLF package
10
on a relatively large (compared to the MLF package proper) support substrate
20
, the bottom surface
15
of the substrate
11
abuts against an arrangement of (thermally and electrically) conductive vias
21
, that extend to a heat dissipation region or medium
22
(such as a metallic plate) of substantial area on the underside of the support substrate
20
.
It is often the case that a given circuit architecture, such as but not limited to a SLIC, will be implemented using a plurality of such MLF packages mounted to a common support member, such as the support substrate
20
of FIG.
1
. Moreover, the overall circuit architecture may be designed to operate at a plurality of different parameter settings, including the use of different DC voltages for different circuit functions. As a non-limiting example, a SLIC may employ a variable battery supply unit that provides for the selectivity of a high battery voltage (e.g., on the order of −125 VDC), or a low battery voltage (e.g., on the order of −60 VDC), depending upon the intended functionality of the circuit (e.g., voice signaling vs. ringing). In such an architecture, there is a concern that an initially selected battery voltage to back-bias the various IC substrates may become less than the maximum available, where the applied DC voltages are subject to change.
SUMMARY OF THE INVENTION
In accordance with the present invention, this problem is successfully addressed by a reduced complexity, diode coupling-based technique, that is effective to back-bias each of the semiconductor substrates of a plurality of integrated circuits at the maximum (e.g., most negative for N-type semiconductor material) of all DC voltages being applied to the circuit, irrespective of a variation in which voltage is the maximum voltage at any particular time.
For this purpose, each semiconductor chip/substrate is augmented to include an auxiliary voltage terminal that is conductively connected to the underside biasing and thermal dissipation pad of the substrate. Where each integrated circuit is formed in a separate chip, there will be a separate auxiliary voltage terminal for each circuit. Where multiple circuits are formed in a common substrate, the substrate will contain a single auxiliary voltage terminal associated with all of the circuits.
Multiple DC voltage terminals are diode-coupled to a common node feeding an associated auxiliary voltage terminal. In addition, the common node is coupled to the auxiliary voltage terminal through a relatively large valued resistor. The use of a large valued coupling resistor between the common node and the auxiliary voltage terminal serves to comply with safety standards, in the event of a ground fault to a metallic dissipation layer of an underlying support structure on which the semiconductor substrate is mounted, by effectively minimizing current flow to any of the DC voltage terminals. For biasing an N-type semiconductor substrate at the most negative DC voltage, the diodes are connected to the common node in a back-to-back configuration.
This diode-coupling arrangement ensures that the voltage at the auxiliary voltage terminal will always be the most negative of all the DC voltages applied to the plural voltage terminals for the substrate, so that the substrate will be back-biased at the most negative DC voltage applied to any and all of the integrated circuits it contains. In an MLF package, the auxiliary voltage terminal is connected to the substrate's underside pad. With multiple MLF packages mounted and conductively joined to a shared metallic dissipation region of a support substrate, all of the auxiliary voltage terminals will be connected in common. This causes the underside pad of each semiconductor substrate to acquire the most negative of all DC voltages applied.
REFERENCES:
patent: 3868594 (1975-02-01), Cornwell et al.
patent: 3892596 (1975-07-01), Bjorklund et al.
patent: 4307307 (1981-12-01), Parekh
patent: 6574652 (2003-06-01), Burkhard
patent: 2002/0134419 (2002-09-01), Macris
patent: 2003/0143958 (2003-07-01), Elias et al.
patent: 2003/0179549 (2003-09-01), Zhong et al.
patent: 3-55897 (1991-01-01), None
Enriquez Leonel E.
Youngblood Douglas L.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Intersil America's Inc.
Williams Alexander Oscar
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