Arrangement for apportioning priority among co-operating compute

Details Arrangement for apportioning priority among co-operating compute Arrangement for apportioning priority among co-operating compute

1986-06-27

1988-12-13

Chan, Eddie P.

Boots, shoes, and leggings

34082551, G06F 1318

Patent

active

047915633

DESCRIPTION:

BRIEF SUMMARY
FIELD OF INVENTION

The invention relates to a priority apportioning arrangement for computers containing processors of two types, namely a first high-priority type which can determine its priority itself in relation to processors of a second low-priority type when using a common bus, the arrangement being such as to allow the use of the bus by the low-priority type if the high-priority processor does not have important tasks.


BACKGROUND

In a system having several processors using the same bus where none of the processors has priority, distribution on the bus can take place with the aid of logic which obtains a signal from each of the prospective users and assigns the bus to them in a given order, with the latest user coming last. None of the processors can be kept out longer than for a number of accesses corresponding to the number of processors minus one.
Apportioning becomes more complicated when a number of processors with low priority and a processor with high priority work on the same bus. In known arrangements such as that described in Electronic Design, May 24th, 1978, extra time is necessary for assigning the bus when the high-priority processor needs it.


SUMMARY OF INVENTION

An object of the invention is to shorten the waiting time and to give a high-priority processor full priority when it needs the bus, but to give access to associated low-priority processors when the bus is not needed by the high-priority processor.
This is achieved in accordance with the invention by blocking access to the bus for the low-priority units when the high-priority one needs the bus, whereas when the high-priority unit does not need the bus immediately, the low-priority units are given access for a time in given proportion to the operating time of the high-priority unit.
In accordance with the invention there is provided a computer system which comprises a bus, a memory coupled to the bus, a plurality of processors, including high-priority processors and low-priority processors and access circuits for selectively coupling the high and low-priority processors via the bus to the memory according to a priority arrangement. The low-priority processors are capable of selectively generating responsive request-for-bus-access signals. Further includes in a program selector arrangement capable of generating a first signal which ultimately results in a reverse bus signal for coupling the high-priority means via the bus to the memory and a second signal allowing access to the low priority processors. The processors are further capable of generating bus-occupied signals.
The access circuit includes first and second logic circuits. The first logic circuit includes first, second and third inputs for respectively receiving request-for-bus-access signals from the low-priority processors, a second input signal and a bus-occupied signal. The first logic circuit furthermore includes first and second outputs for transmitting access-to-low-priority-processors signals and access-to-high-priority-processors signals. The second logic circuit includes first and second inputs for receiving the first and second signals respectively from the program selector arrangement and it further includes a third input coupled to the second output of the first logic circuit. The second logic circuit generates the reserve-bus signal and one of the bus-occupied signals and further includes first and second outputs for respectively transmitting the latter said signals to the second and third inputs of the first logic circuit. The first output of the first logic circuit is coupled to the low-priority-processors for accessing the latter respectively via the bus to the memory. The second output of the first logic circuit is coupled to the high-priority-processors to couple the same via the bus to the memory.
Other objects, features and advantages of the invention will be found in the Detailed Description which follows hereinbelow.


BRIEF DESCRIPTION OF DRAWINGS

The invention will be described below with reference to the accompanying drawings, in which:

REFERENCES:
patent: 4096569 (1978-06-01), Barlow
patent: 4121285 (1978-10-01), Chen
patent: 4151592 (1979-04-01), Suzuki et al.
patent: 4257095 (1981-03-01), Nadir
patent: 4271467 (1981-06-01), Holtey
patent: 4302808 (1981-11-01), Zanchi et al.
Soe Hojberg, K., "One-Step Programmable Arbiters for Multiprocessors", Computer Design, Apr. 1978, pp. 154-158.

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