Arrangement for adjusting an impedance network in an integrated

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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307270, 357 51, H01L 2702, G05F 500

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active

047975784

ABSTRACT:
An integrated semiconductor circuit has the impedance networks (R11, R12, R13; R21, R22, R23) which can be adjusted with adjustment impedances (R14, R15; R24, R25). These are connected with the aid of adjustment circuits including a thyristor (TY1-TY4) and a short-circuiting zenerdiode (ZZ1-ZZ4). To avoid extra terminals for the adjustment circuit this is connected between two current terminals (6, 7) necessary for the normal operation of the semiconductor circuit. The electrode (11) of the thyristor (TY1-TY4) is connected to a signal input (E0-E3) which is also necessary for the normal operation. During adjustment, a voltage source is connected to one of the signal inputs (E0-E3) so that the corresponding thyristor (TY1-TY4) will become conductive and a current source is connected between the current terminals (6, 7). The current short-circuits the corresponding zenerdiode (ZZ1-ZZ4) so that the adjustment impedance is connected in parallel. The integrated circuit and its connection lines (12, 13, 14) are intended to withstand in normal operation the voltages and currents present during adjustment. The arrangement allows impedance adjustment of a ready-encapsulated integrated circuit, merely the exterior terminals needed for the normal operation of the circuit being utilized. Extra exterior terminals requiring room on a circuit board are avoided.

REFERENCES:
patent: 4225878 (1980-09-01), Dobkin
patent: 4412241 (1983-10-01), Nelson
patent: 4460914 (1984-07-01), te Velde et al.
"A Precision Trim Technique for Monolithic Analog Circuits", George Erdi, IEEE Journal of Solid State Circuits, vol. SC10, No. 6, Dec. 1975 (pp. 412-416).

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