Arrangement for addressing a MOS store

Details Arrangement for addressing a MOS store Arrangement for addressing a MOS store

1977-09-14

1978-08-01

Hecker, Stuart N.

Static information storage and retrieval

Addressing

307205, 307DIG5, G11C 800

Patent

active

041047354

ABSTRACT:
A system is disclosed for addressing a MOS store containing MOS transistor storage cells. Address signals are amplified, inverted and intermediately stored. Negated and non-negated address signals are fed to a decoder circuit connected by drive lines to the storage cells. The decoder circuit selects a drive line depending upon the prevailing address signals. The decoder circuit is provided as a preliminary decoder circuit and a post decoder circuit. The preliminary decoder circuit has a plurality of stages wherein each stage is supplied with address signals in negated and non-negated form. Output lines of the preliminary decoder stages are connected to the post decoder circuit. Drive lines connect the storage cells to the post decoder circuit. Logic linking elements are provided in the post decoder circuit for logic linking these drive lines to the output lines of the preliminary decoder stages.

REFERENCES:
patent: 3902082 (1975-08-01), Proebsting et al.

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