Computer graphics processing and selective visual display system – Computer graphic processing system – Plural graphics processors
Patent
1997-02-14
1999-11-09
Coleman, Eric
Computer graphics processing and selective visual display system
Computer graphic processing system
Plural graphics processors
345524, G06F 1516
Patent
active
059823933
DESCRIPTION:
BRIEF SUMMARY
FIELD OF THE INVENTION
The present invention relates to a device in a parallel processor containing a number of processor elements of the same type which are integrated on one and the same semiconductor chip, and which are of the kind that allows parallel image or signal processing of the information stored in the processor element, whereby the said device contains a unit block for each processor element.
BACKGROUND OF THE INVENTION
In data-type image processing, high demands are made on a very fast performance of the image-associated operations. A way of achieving a high processing speed is to use units with an integrated unit solution comprising both a camera in the form of a photodiode matrix and an image processor. Such an arrangement is known from, e.g., SE, B, 431 145 which presents an image processor which contains a device able to indicate the image dots belonging to a connected object, and produces a binary signal corresponding to the object when the relevant image dot, on the one hand, meets a condition specific to the object, and, on the other hand, is indicated as entering the object, or when the closest adjacent image dots are distinguished. By means of this known technique the need is reduced for a serial output of image data, and a substantially reduced amount of information is obtained which, with less time consumption than for the known image processing systems, can be output for further image processing.
Another example of corresponding parallel signal processing is described in Swedish Patent No. 9001556-1. The intention here is to be able to carry out computations on radar signals in addition to image processing.
A drawback with the known technique is that the known processors cannot perform so-called arithmetic global operations with the same efficiency, for example determine the centre of median for every object in a read-in vector. In the known device, there takes place with this type of operation a serial outputting of image data which, in per se time terms, reduces the advantages of the fast image processors.
SUMMARY OF THE INVENTION
The object of the present invention is to obviate this drawback and to provide a processor wherein each processor element is connected with a unit block which makes arithmetic global operations possible. This object is achieved in that each unit block comprises at least two incrementing units which are designed to add a signal supplied to the unit block, and a signal which originates from an incrementing unit corresponding to the respective unit in the closest preceding unit block in every direction of the processor element matrix, and in that every unit block further contains at least one logical unit which is designed to perform logical operations of Boolean type on the signals received from the incrementing units of the unit block.
According to a characteristic of the invention, said signal supplied to the unit block corresponds to an image or radar signal coming from a processor element.
According to a particular characteristic of the invention, the number of incrementing units in every unit block is two, and the device is preferably designed to be used in line image processing and signal processing.
According to a further particular characteristic of the invention, said incrementing units each contain a plurality of half adders, an AND-gate is connected to one input on the respective half adders, and one input of the AND-gate is connected to the output of the corresponding half adder in the preceding incrementing unit.
According to a further special characteristic of the invention, every incrementing unit contains precisely one half adder over the logarithm of base two of the number of processor elements arranged in line.
According to a last particular characteristic of the invention, said logical unit is designed to compare the values of the incrementing units in every unit block.
BRIEF DESCRIPTION OF THE DRAWINGS
The invention will be explained in greater detail in the following, with reference to the attached drawings wherein
FIG. 1 s
REFERENCES:
patent: 5434968 (1995-07-01), Kunii
patent: 5473750 (1995-12-01), Hattori
patent: 5557734 (1996-09-01), Wilson
patent: 5649106 (1997-07-01), Tsujimichi
Forchheimer Robert
Strom Anders
Coleman Eric
IVP Integrated Vision Products AB
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