Arrangement and process for protecting fuses/anti-fuses

Details Arrangement and process for protecting fuses/anti-fuses Arrangement and process for protecting fuses/anti-fuses

2007-06-26

2007-06-26

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Passive components in ics

C257SE23149

Reexamination Certificate

active

10957492

ABSTRACT:
An arrangement for protecting fuses/anti-fuses on chips which serve to activate redundant circuits or chip functions includes a passivation layer (e.g., hard passivation) arranged on a fully processed chip with the exception of metal contacts of a metallization level and the fuses. The chip is provided with a redistribution layer that is electrically contact-connected to the metallization level, and to a process for protecting such fuses/anti-fuses. The invention is now based on the object of ensuring sufficient protection of fuses/anti-fuses on integrated circuits. This is achieved by virtue of the fact that a dielectric (3.1, 3.2), which covers at least the region of the fuses/anti-fuses (4) and to which the redistribution layer (2) comprising the combination of materials Cu/Ni/Au is applied, is arranged on the passivation layer (5).

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Peter Van Zant, Microchip Fabrication, 4th edition, McGraw—Hill, p. 154.

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