Arrangement and method for transmitting data over a TDM bus

Details Arrangement and method for transmitting data over a TDM bus Arrangement and method for transmitting data over a TDM bus

2006-06-06

2006-06-06

Ton, Dang (Department: 2666)

Multiplex communications

Channel assignment techniques

Combining or distributing information via time channels...

C370S458000, C370S503000, C370S528000, C375S363000

Reexamination Certificate

active

07058073

ABSTRACT:
The invention relates to a TDM backplane bus system, in which a Frame Synchronisation signal is developed from an external communication signal, a data clock signal is produced from a free running clock oscillator independent of the FS signal, to select the frequency of the clock signal so that the number of periods within a frame is always at least one more than the number of timeslots required, to synchronise the FS signal to the CLK signal, and supply this synchronised Frame Synchronising signal (FS-S) to the TDM-bus. Further, the exceeding period(s) is identified by introducing a carry bit in the timeslot counters, the carry bit being set each time the counter(s) exceeds the number of timeslots on the TDM bus.

REFERENCES:
patent: 5088089 (1992-02-01), Gingell et al.
patent: 5483528 (1996-01-01), Christensen
patent: 5544324 (1996-08-01), Edem et al.
patent: 6072796 (2000-06-01), Christensen et al.
ECTF; Hardware Compatibility Specification: CT Bus, revision 1.0.
ITU-T Recommendation G.705(Oct. 2000); Characteristics of plesiochronous digital hierarchy (PDH) equipment functional blocks.

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