Arrangement and method for the transmission of address,...

Data processing: generic control systems or specific application – Generic control system – apparatus or process – Plural processors

Reexamination Certificate

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Details

C710S110000

Reexamination Certificate

active

06418349

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to an arrangement which includes a control unit (master) and at least one controlled unit (slave) for the transmission of address, instruction and/or data telegrams from the control unit to the (at least one) controlled unit (units) and for the return of a respective reception acknowledge signal from the controlled unit (units) to the control unit in response to each of the address, instruction and/or data telegrams, the reception acknowledge signal signaling the control unit the correct transmission of the relevant address, instruction and/or data telegram.
The invention also relates to a method for the transmission of address, instruction and/or data telegrams from a control unit to (at least) one controlled unit and for the return of a respective reception acknowledge signal from the controlled unit (units) to the control unit in response to each of the address, instruction and/or data telegrams, the reception acknowledge signal signaling the control unit the correct transmission of the relevant address, instruction and/or data telegram.
Arrangements and methods of this kind are employed in so-called I
2
C bus systems, so control and data bus systems which are preferably used for the control and the exchange of data in complex electronic communication arrangements, preferably in entertainment electronics. Such I
2
C bus systems notably interconnect circuit sections accommodated in different integrated semiconductor circuits. The control unit (master) can thus transmit data or instructions to one or more controlled units via the bus. The controlled units require a bus receiver stage for this purpose.
However, if data is to be transmitted also from the controlled units (slaves) to the control unit (master), the controlled units should also be provided with a bus transmitter stage. A combined bus receiver stage and bus transmitter stage (transceiver) requires approximately from 30 to 40% more components than a bus receiver stage alone. If the controlled units are to transmit data to a limited extent only, providing the relevant integrated semiconductor circuit with a bus transmitter stage for this purpose alone would be very uneconomical because of the associated larger surface area required on the semiconductor body.
OBJECTS AND SUMMARY OF THE INVENTION
It is an object of the invention to conceive an arrangement and a method of the kind set forth in such a manner that data can be transmitted to the control unit to a limited extent also without providing bus transmitter stages in the controlled units.
This object according to the invention is achieved in an arrangement of the kind set forth in that at least one of the controlled units is constructed in such a manner that the reception acknowledge signal in response to at least one of the address, instruction and/or data telegrams is suppressed, exclusively in dependence on a selectable parameter of the operating state of the controlled unit, also in the case of correct transmission of the address, instruction and/or data telegram, the control unit in that case always being signaled an incorrect transmission, and that the control unit includes an evaluation section in which the nonarrival of a reception acknowledge signal in response to said address, instruction and/or data telegram is received and processed as an information signal concerning the selectable parameter of the operating state of the controlled unit.
According to the invention, moreover, the method of the kind set forth is characterized in that in (at least one) controlled unit (units) the reception acknowledge signal in response to at least one of the address, instruction and/or data telegrams is suppressed, exclusively in dependence on a selectable parameter of the operating state of the controlled unit, also in the case of correct transmission of the address, instruction and/or data telegram, the control unit in that case always being signaled an incorrect transmission, and that the nonarrival of a reception acknowledge signal in the control unit in response to said address, instruction and/or data telegram is evaluated as an information signal concerning the selectable parameter of the operating state of the controlled unit.
Thus, according to the invention the reception acknowledge signal from the relevant controlled unit addressed by the control unit is used not only to acknowledge the correct transmission of the address, instruction and/or data telegram but, without using additional circuit means, but also to return information to the control unit. The functions required for this purpose are incorporated in the components of the control unit and the controlled unit (units) which are required any way for the sequencing of the instruction and/or data transmission between said units. Special address, instruction and/or data telegrams can be provided in response to which a given parameter of the operating state is tested in the relevant addressed controlled unit, or possibly also in a plurality of controlled units simultaneously, and the associated reception acknowledge signal is returned or not, depending on the result of said test. Using a fixed preset within the controlled unit (units), a given parameter of the operating state can then be interrogated in principle, for example whether the supply voltage reaches a given threshold value or not. On the basis of the type of transmitted address, instruction and/or data telegram, however, a selection between a plurality of parameters to be tested in respect of the operating state of the controlled unit (units) can be made in the controlled unit (units). For example, state registers can thus be interrogated. This interrogation can be selected on the one hand by encryption within the address, instruction and/or data telegram or be performed successively for the parameters of interest in conformity with a predetermined instruction sequence. In order to execute the instruction sequences required for this purpose, the control unit includes an evaluation section which may be constructed as a separate logic circuit or is preferably included in a sequencer which is provided any way for the transmission of the address, instruction and/or data telegrams. The nonarrival of a reception acknowledge signal is detected in said evaluation section as information concerning the selected parameter of the operating state of the addressed controlled unit (units). To this end, the evaluation section preferably comprises an instruction sequencer which may involve control instructions whereby the detected operating state can be deliberately changed, if desired.
The invention thus enables an expansion of the information exchange between the control unit and the controlled unit (units), without it being necessary to provide the controlled unit (units) with an additional transmitter stage (stages) for the transmission of address, instruction and/or data telegrams to the control unit. A large number of circuit elements is thus saved. The invention is particularly attractive for the return transmission of merely small quantities of data for which the separate transmitter stages in the controlled units would not be used to full capacity. The invention can be used particularly advantageously for the interrogation of predetermined parameters with a response in the form of yes-no information. In an embodiment of the arrangement according to the invention each controlled unit (units) comprises (comprise) a respective monitoring device for monitoring the parameter or the parameters of the operating state and for suppressing the reception acknowledge signal in response to a selectable address, instruction and/or telegram, in dependence on the monitored parameter or parameters of the operating state.
A monitoring device of this kind preferably includes one or more state registers which are associated with the parameters of the operating state to be monitored and store information as regards the instantaneous value of the relevant parameter. Using especially encoded address, instruction and/or data te

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