Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
1999-03-17
2002-09-24
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C257S763000
Reexamination Certificate
active
06455937
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of integrated circuits and integrated circuit manufacturing. More particularly, the present invention relates to the interconnection of electronic circuit structures and to blocking diffusion of high-conductivity structures using a thin barrier layer that is useable in downwardly scaled semiconductor structures.
BACKGROUND OF THE INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. Such silicon-based semiconductor devices often include metal-oxide-semiconductor (MOS) devices, such as p-channel MOS (PMOS), n-channel MOS (NMOS), complimentary MOS (CMOS), BiCMOS devices, and bipolar transistors. Each of these semiconductor devices generally includes a semiconductor substrate on which a number of active devices are formed and connected to other circuitry using metal interconnects extending from metal layers formed above the devices. The particular structure of a given active device can vary between device types. For example, a MOS transistor generally includes source and drain regions and a gate electrode that modulates current between the source and drain regions. Depending on the circuit design, one or more metal layers are formed above such MOS transistors with lower level metal interconnects extending to various portions of the MOS transistors, such as to the gate electrodes and the source/drain regions.
In the past, the metal interconnects have been typically formed from aluminum alloys. By the late 1 990s, other metals, including copper, have been increasingly used and considered because of their improved conductivity and improved resistance to electromigration.
One important step in the manufacture of such devices is the formation of barrier or isolation regions to prevent diffusion from the metal layers to the active areas of the semiconductor devices. Diffusion occurs at elevated temperatures where there is a concentration gradient between dopant atoms external to a region of the silicon wafer and dopant atoms in the silicon wafer region. Diffusion is problematic in a number of areas including, for example, in copper-based interconnect systems processed using technologies below about 0.25 &mgr;m and the “dual-Damascene” approach, where vias and metal lines are formed simultaneously into dielectric slots. To prevent copper diffusion into the active area of the device, various barrier metal or metal-compound films have been used including, for example, Ta and TaN at barrier thicknesses of about 300 Å to 500 Å. Preventing diffusion of copper is important, because the presence of copper in the substrate silicon causes an increase in pn junction leakage and threshold voltage shifts in MOS devices. Such diffusion has also caused reduced dielectric breakdown.
As downward scaling of semiconductor structures continues and processing approaches 0.06 &mgr;m (600 Å) levels, for example, conductive barrier films having thicknesses in the range of 300-500 Å will be prohibitively thick to the practical manufacture of such semiconductor structures. For example, a via having a width of 0.06 &mgr;m would be filled completely with a barrier film coating of only 300 Å in thickness. Further, because the resistivity of many barriers materials is quite high, a significant increase in sheet resistivity (“Rs”) for copper lines, formed by the Damescene process, would occur with even thinner barriers. The resistivity of TaN, for example, is about 150 times higher than the resistivity of copper.
For such small via structures, in addition to the sidewall barrier thickness being a concern, the barrier material at the base of the opening would cause an increase in via resistance. For example, the resistance across the barrier in a 0.06 &mgr;m wide via using a 300 Å TaN bottom coating would be about 20 ohms.
While the above discussion evidences the need to reduce the barrier thickness for downwardly scaled semiconductor structures, an analysis of prior art suggests that the thickness of certain barrier materials against diffusion of the highly-conductive metals (such as copper and silver) can be reduced to thicknesses to about 100 Å without adversely impacting circuit operation. A more detailed analysis of published data on bias/temperature studies, on the effect of barrier thickness on dielectric failure (high leakage), suggests that for TaN barriers, a rough estimate for a minimum barrier thickness is on the order of 20 Å. This estimate is based on a number of assumptions that may or may not be applicable for a given application. Among others, these assumptions include: a median time to failure t
50
of about 10
6
hours is needed at an operating temperature of 150° C., (consistent with a long term failure percent of 0.1 at 10
6
hours and a log normal sigma of 0.8), and an acceleration factor to 275° C. (estimated on the basis of the activation energy of Cu diffusion in Cr). The temperature of 275° C. is the level at which there have been relevant studies of dielectric failure due to copper diffusion, with reported data on the median time to failure (t
50
) for several thickness of TaN. For further information concerning such work, reference may be made to VMIC Conference Proceedings, June 10-12, 1997. p.87. The test device employed in this work was under an electric field of 2 MV/cm. This data can be plotted as t
50
versus the barrier thickness ‘x’ yielding the relationship:
t
50
=k
x,
where k=0.23 hours/Å.
Using the above target value of t
50
and the acceleration factor, a minimum barrier thickness for TaN is estimated to be on the order of 20 Å.
At the less aggressive operating temperature of 125° C., according to the present invention, an analysis based on the above reasoning suggests that a barrier on the order of a single monolayer would suffice. Thus, the very thin barrier films suggested in connection with the present invention would range from less than 60 Å to a monolayer of material depending, of course, on the diffusion coefficient (D) of the barrier.
The above estimate is for a sufficient barrier thickness to protect the dielectrically-insulated interconnects, where electric fields on the order of 2×10
5
V/cm might be present. The diffusion rate of copper is greatly accelerated by an electric field, but with a conductive barrier in place, the amount of copper transported into a dielectric is controlled by thermal diffusion rates only. But to protect underlying active devices and pn junctions, additional protection is necessary.
One prior art approach for forming copper-based interconnects or vias is illustrated in
FIGS. 1A-1C
. Beginning with
FIG. 1A
, the approach involves a plasma etching process to open a trench
110
through a SiN layer
112
and through an underlying SiO
2
-based dielectric layer
114
. The plasma etching process terminates when the trench
110
reaches a conductive contact region
116
under the SiO
2
-based dielectric layer
114
. As shown in
FIG. 1B
, a barrier layer
120
of sufficient thickness to protect underlying active transistors is then formed, followed by sputter deposition or electroplating of copper
122
. A chemical-mechanical polishing (CMP) process is then used to planarize the structure down to the top of the SiN layer
112
. The polished structure is shown in FIG.
1
C. The SiN layer
112
acts as a hard polishing stop for the CMP process, and also inhibits copper diffusion into lower levels from the copper source and from any copper interconnects above the one shown in FIG.
1
C.
One problem with thi
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Cao Phat X.
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