Optics: measuring and testing – By alignment in lateral direction – With registration indicia
Reexamination Certificate
1999-03-08
2001-10-09
Evans, F L (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
With registration indicia
C356S400000, C250S559300
Reexamination Certificate
active
06301008
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and their manufacture and, more particularly, to arrangements and processes for developing relatively narrow linewidths of elements such as gate lines, while maintaining accuracy in their fabrication.
BACKGROUND OF THE INVENTION
The electronics industry continues to rely upon advances in semiconductor technology to realize higher-functioning devices in more compact areas. For many applications, realizing higher-functioning devices requires integrating a large number of electronic devices into a single silicon wafer. As the number of electronic devices per given area of the silicon wafer increases, the manufacturing process becomes more difficult.
An important part of semiconductor processing is the capability of the optical lithographic process. Optical lithography is used to create semiconductor elements, including those having such narrow linewidths. Optical lithography involves the creation of images of one or more circuit elements or features and projecting those elements or features onto a semiconductor wafer.
Due to the smaller geometries used in today's semiconductors, there has been less tolerance for dimensional anomalies and related geometry inaccuracies. Like other fabrication equipment used in the manufacture of today's semiconductors, optical lithography equipment contributes to such anomalies and inaccuracies. Consequently, optical lithography equipment is regularly checked and measured to ensure that the images being obtained and used from the optical lithography equipment are as true as possible.
One common method for making such checks and measuring discrepancies involves the definition of a traditional box-in-box structure. Such a structure has an outside box of about 20 &mgr;m square defined by a line or trench and a centrally disposed inside box of about 10 &mgr;m square similarly defined by a line or trench. In either case, the box-in-box configuration utilizes measurements between edges of the boxes. It will be understood that the capability of the overlay metrology tool to recognize the edges of boxes is sometimes limited by the discernibly of the box edges, by contrasts and differences in color shading at the box edges, and by the ability of the overlay metrology tool to distinguish junctions defining a solid square rather than merely a line configuration, such as a pattern of laterally spaced lines.
In some instances, such as defined in the above identified parent application, it is useful to take calibrating measurements of lines that, when printed, are narrow enough to be shortened to the same degree that the feature lines of the finished circuit will be shortened. The degree of line shortening can then be determined and the dimensions of the mask feature can be accurately lengthened to compensate for the expected line shortening when the mask is used to create the line feature on the resist. In addition to lengthening the mask line, other forms of line shortening corrections may be used. Examples include the use of enlargements at the ends of the lines in the form of hammerheads or various other forms of serifs. Very small island features (also known as pillar features) have the same shortening effect as narrow lines, but in two dimensions rather than one. Many of the same forms of correction used to correct line shortening can also be used to correct the shortening of both dimensions of islands.
In many instances, the individual features of a circuit, such as the gate lines, have extremely small dimensions and may have widths of less than 0.2 &mgr;m to 0.4 &mgr;m with their lengths being considerably greater, perhaps 0.8 &mgr;m to 2.0 &mgr;m. Moreover, the thin gate lines may well be intended for connection to other layers of the integrated circuit by way of narrow vias filled with electrically conductive material. When dimensions reach such small size, there is not only a tendency for the formed line to be shorter than its design length as defined by the mask, but also the positioning of the vias may not be aligned to the target structure(s). Transfer differences of such critical dimension occurs when a desired circuit feature is particularly thin or small because of optical diffraction effects. As feature sizes get smaller, diffraction defects increase.
To maintain the accuracy of narrow linewidths during the optical lithograph process, optical proximity correction (OPC) systems are typically used. One form of OPC is to utilize masks which include images that are distorted to an outline that is different from the outline of the desired feature. This difference is used to reverse the anticipated distortion that would otherwise result from the printing system. One example of OPC is to provide a mask having the outline of a narrow line feature lengthened as compared to the length of the line “as drawn” (the intended length of the feature on the resist). Such OPC systems are extremely beneficial. However, in the fabrication of integrated circuits (ICs) having relatively narrow linewidths on different levels of the circuit, with the linewidth elements interconnected by conductive material deposited in vias extending between levels, the accuracy of forming and positioning the lines and the vias becomes increasingly critical. Relatively minor errors in positioning such features can cause a via to miss the line altogether or to contact the line over a surface area that is insufficient to provide the necessary conductivity for a fully-functional circuit.
FIGS. 1A
,
1
B and
1
C illustrate an aspect of the problem discussed above for a modified box-in-box structure. These figures show a mask (
FIG. 1A
) for the box-in-box structure, a scanning electron microscope (SEM) photograph (
FIG. 1B
) of a photoresist formed using the mask of
FIG. 1
a,
and an optically-acquired image (
FIG. 1C
) of a structure implemented onto a wafer using the photoresist of FIG.
1
B. When projecting the lines of the structure of
FIG. 1A
onto a positive resist, as shown in
FIG. 1B
, the length of the imaged line is somewhat smaller than the corresponding mask feature. The left and bottom portions of the structure of
FIG. 1A
are large blocks of metal while the top and right are constructed from sub half-micron lines and spaces. While the large blocks will transfer their geometries with minimal distortion, the lines and space patterns will be somewhat truncated depending on their line width. If the resulting pattern (
FIG. 1C
) is viewed optically, the sections constructed of gratings will not be resolved into discrete lines and spaces but will appear as a solid blocks.
FIG. 1C
shows these line endings of the grating sections as a single edge. Truncation should have the effect of apparently shifting the center box towards the grating sections with misalignment being a relative measure of the truncation.
Accordingly, the ability to manufacture within relatively narrow lines using optical lithography is an important aspect of semiconductor processing. Such processing continues to be burdened by inaccuracies from the stage involving optical measurements of the extremely narrow linewidths to the practical implementation stage where the characterized linewidths are used to build narrow linewidth elements in a sub-micron process. For such semiconductor manufacturing processes and arrangements, it would be helpful to determine the effect of and to account for line shortening using optical measurements.
SUMMARY
According to various aspects of the present invention, embodiments thereof are exemplified in the form of methods and arrangements for fabricating semiconductor structure using Optical End of Line Metrology (OELM) and an optical alignment measurement tool calibrated as a function of a pitch effect and a determined relationship. Relative line shortening effects are inherent in many semiconductor fabrication processes that use optical line measurements to image a frame onto a wafer. For example, when imaging a frame onto a wafer where the frame has two adjacent sides constructed of lines and spa
Leroux Pierre
Ziger David
Crawford PLLC
Evans F L
Philips Semiconductor Inc.
Smith Zandra V.
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