Arrangement and construction of an output control circuit in a s

Details Arrangement and construction of an output control circuit in a s Arrangement and construction of an output control circuit in a s

1988-11-22

1990-11-27

Gossage, Glenn

Static information storage and retrieval

Interconnection arrangements

36518905, G11C 506, G11C 700

Patent

active

049742035

ABSTRACT:
A semiconductor memory device includes output control circuits which are located adjacent to column sense amplifiers and output transistors which are located at a distance from the output control circuits. The wiring length of a first wiring from the column sense amplifiers to the output control circuits is set to be shorter than the wiring length of a second wiring from the output control circuits to the output transistors. The second wiring has a parasitic capacitance at least five times the parasitic capacitance of the first wiring.

REFERENCES:
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4602353 (1986-07-01), Wawersig et al.
patent: 4604731 (1986-08-01), Konishi
patent: 4827454 (1989-05-01), Okazaki
patent: 4831590 (1989-05-01), Ichinose

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