Arithmetical unit including accumulating operation

Details Arithmetical unit including accumulating operation Arithmetical unit including accumulating operation

1993-01-27

1994-12-20

Baker, Stephen M.

Boots, shoes, and leggings

364768, G06F 738, G06F 750

Patent

active

053750799

ABSTRACT:
An improved M-bit accumulator for increasing speed and reducing circuit size includes an N-bit (N<M) adder, a first latch having an input coupled to the output of the adder and an output coupled to an input of the adder for latching the adder output when a first clock signal is asserted, an (M-N) bit incrementer, a second latch having an input coupled to the output of the incrementer and an output coupled to the input of the incrementer for latching the incrementer output when a second clock signal is asserted, and a clock generating circuit for asserting the second clock signal in synchronism with the first clock signal only when a carry signal is generated by the adder.

REFERENCES:
patent: 4719589 (1988-01-01), Tanaka
patent: 5040136 (1991-08-01), Kanoh
patent: 5208770 (1993-05-01), Ito
Patent Abstracts of Japan, vol. 2, No. 88 (E-044) Jul. 19, 1978 (JP-A-53051936, Hitachi Seisakusho KK) May 11, 1978.
IBM Technical Disclosure Bulletin, vol. 32, No. 1, Jun. 1989, New York, N.Y. PP. 13-14 XP000033229, "High Speed Incrementer".
Electronic Engineering, vol. 49, No. 588, Feb. 1977, London, GB, p. 18, "Accumulating Adder Works with Reversible Counter," K. Westowski.
IBM Technical Disclosure Bulletin, vol. 21, No. 3, Aug. 1978, pp. 1082-1083, "Sum of Absolute Values under Control of ALU Sign Bit," J. Beraud, et al.
Patent Abstracts of Japan, vol. 7, No. 249, p. 234, Nov. 1983 (JP-A-58132861, Tokyo Shibaura Denki KK) Aug. 1983.
IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, 1986 "A Digital Processor for Decoding Composite TV Signals Using Adaptive Filtering," Kenji Murakami, et al.
IEEE 1990 Custom Integrated Circuits Conference "A Flexible Motion-Vector Estimation Chip for Real-Time Video Codecs," Yang, et al.

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