Arithmetic unit with simple overflow detection system

Details Arithmetic unit with simple overflow detection system Arithmetic unit with simple overflow detection system

1986-04-15

1988-08-30

Harkcom, Gary V.

Boots, shoes, and leggings

364749, G06F 738

Patent

active

047681608

ABSTRACT:
An arithmetic unit with a simple overflow detection system performs arithmetic operations between first and second data. The first data is exclusively divided into a fixed value portion and a variable portion, whose digit position is lower than that of the fixed value portion. The ratio of a length of the fixed value portion to that of the variable portion in the first data varies. The second data corresponds only to the variable portion of the first data. The arithmetic unit includes an adder for adding the first and second data in their entire lengths, a switch circuit for separating output data from the first data and the adder into fixed value and variable portions, a comparator for comparing the fixed value portions of the outputs from the first data and the adder and outputting a coincidence or noncoincidence signal, an output register for linking the fixed value portion of the first data and the variable portion of the output from the adder and outputting the linked data, and an overflow detector for detecting an overflow in response to the noncoincidence signal from the comparator.

REFERENCES:
patent: 4437165 (1984-03-01), Onodera
Rosenfeld, J. L., "Variable-Width Adder for Microprogrammed Computers Used for Emulation", IBM Technical Disclosure Bulletin, vol. 15, #4, pp. 1149-1150, Sep. 1972.
Arithmetic Operations in Digital Computers, R. K. Richards, Van Nostrand Co., Inc., 1955, pp. 81-135.
The Logic of Computer Arithmetic, Ivan Flores, Prentice-Hall Inc., pp. 70-83.
Digital Computer Design, Edward L. Braun, Academic Press, 1963, pp. 266-371.

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