Arithmetic unit with alternate mark inversion (AMI) coding

Details Arithmetic unit with alternate mark inversion (AMI) coding Arithmetic unit with alternate mark inversion (AMI) coding

1987-12-08

1989-08-22

Harkcom, Gary V.

Boots, shoes, and leggings

364769, 3401462, G06F 738

Patent

active

048602353

ABSTRACT:
An arithmetic unit having true and false deciding circuits (21 to 24) for receiving a first input signal A and a second input signal B to output the second input signal or complement of the same in response to the sign (most significant bit value) of the second input signal. The arithmetic unit further includes an adder (31 to 34) for receiving the first input signal A and output (M) from the true and false deciding circuits to output either A+M or A+M+1 in response to the sign (most significant bit value) of the second input signal B and an AND gate (50) for receiving the most significant bit F.sub.4 of output F from the adder and the most significant bit value B.sub.4 of the second input signal B. The arithmetic unit thus outputs the alternate mark inversion (AMI) code of the input signal B having the output of the AND gate (50) as a high order bit and the most significant bit F.sub.4 of the output F of the adder as a low order bit, with a threshold value of the input signal A.

REFERENCES:
patent: 3434109 (1969-03-01), Coote
patent: 3955177 (1976-05-01), Miller
patent: 4767949 (1988-08-01), Mayweather, III
Mano, "Digital Logic and Computer Design", Prentice Hall, 1979, Chapter 2, Sections 2.4 and 2.6.
Ho et al., "Comparator Compares 2's Complement Numbers", Electronics, Aug. 25, 1983, pp. 138-139.

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