Arithmetic unit for use in a digital data processor and having a

Details Arithmetic unit for use in a digital data processor and having a Arithmetic unit for use in a digital data processor and having a

1975-06-23

1976-10-12

Dildine, Jr., R. Stephen

Registers

Transfer mechanism

Traveling pawl

235153BN, 3401461AG, G06F 1110, H04L 110, H03K 1334

Patent

active

039860159

ABSTRACT:
A digital arithmetic unit employing a binary adder for adding and subtracting multidigit binary coded decimal numbers in either zoned format or packed format and having an improved method of generating parity check bits for the resultant data bytes produced by the arithmetic unit. When using a binary adder for adding or subtracting binary coded decimal numbers, it is necessary to correct some of the data appearing at the output of the binary adder in order to obtain the correct results. The parity check bit generating circuitry of the present invention, however, works on the uncorrected data appearing at the output of the adder, but nevertheless produces the proper parity check bits for the corrected data which represents the final output for the arithmetic unit. This reduces the amount of time delay which would otherwise be caused by generating the parity check bits in a conventional manner.

REFERENCES:
patent: 3051387 (1962-08-01), Pomerene et al.
patent: 3235854 (1966-02-01), Nugent
patent: 3287546 (1966-11-01), Geller
patent: 3300625 (1967-01-01), Deng et al.
patent: 3342983 (1967-09-01), Pitkowsky
patent: 3596072 (1971-07-01), Iwamoto
Dellacato, F. C. Simplified Parity Check Circuitry in IBM Tech. Disc. Bull. 3(11): pp. 25-26, Apr. 1961.

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