Arithmetic unit for use in a data processing system for computin

Details Arithmetic unit for use in a data processing system for computin Arithmetic unit for use in a data processing system for computin

1981-04-23

1984-01-31

Malzahn, David H.

Boots, shoes, and leggings

364745, G06F 748

Patent

active

044293704

ABSTRACT:
A data processing system using unique procedures for handling various arithmetic operations. Thus, in floating point arithmetic mantissa calculations the system uses a novel technique for inserting a round bit into the appropriate bit of the floating point result wherein a look-ahead carry bit generator stage is used for such purpose to reduce the overall mantissa calculation time. Further, the system utilizes unique logic which operates in parallel with the floating point exponent calculation logic for effectively predicting whether or not an overflow or underflow condition will be present in the final exponent result and for informing the system which such conditions have occurred. Moreover, the system utilizes a simplified technique for computing the extension bits which are required in multiply and divide computations wherein a programmable array logic unit and a four-bit adder unit are combined for such purposes.

REFERENCES:
patent: 3017090 (1962-01-01), Strachey et al.
patent: 4282581 (1981-08-01), Bondurant et al.
patent: 4295203 (1981-10-01), Joyce
Ahearn et al., "Characteristic Overflow or Underflow Detection in Floating Point Operations", IBM Tech. Disclosure Bulletin, vol. 7, No. 8, Jan. 1965, pp. 664-665.
Nguyen, "Practical Hardware Solutions for 2's Complement Arithmetic Problems", Computer Design, Jul. 1979, pp. 105-112.

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