Arithmetic unit for quantization/inverse quantigation

Details Arithmetic unit for quantization/inverse quantigation Arithmetic unit for quantization/inverse quantigation

1994-05-31

1995-07-11

Malzahn, David H.

Boots, shoes, and leggings

36471502, 382251, G06K 936

Patent

active

054327261

ABSTRACT:
Two sets of input data A and B are provided. A first selector circuit outputs either the most significant bit of the input data B or the inversion thereof, in accordance with a control signal which has been sent thereto through a control line. An adder adds 1 to the least significant bit of the input data B, and also adds the output from the first selector circuit to all the other bits thereof. A zero-judgment circuit judges whether the input data B is 0 or not, and then, if it is 0, sets a flag to a predetermined value. A selector-control circuit allows a second selector circuit to select the input data B in the case where the least significant bit of the input data A is 1 or the flag from the zero-judgment circuit is set to the predetermined value, and to select, in the other cases, the output from the adder. In this manner, a conditional branch operation required for quantization and inverse quantization of data is executed at high speed, which operation involves either adding 1 to or subtracting 1 from the input data B to output the result, or outputting the input data B, depending on whether the input data B is positive, negative or zero, and also depending on whether the input data A is an even number or an odd number.

REFERENCES:
patent: 4034196 (1977-07-01), Butterweck et al.
patent: 4569052 (1986-02-01), Cohn et al.
patent: 4775810 (1988-10-01), Suzuki et al.
patent: 5054103 (1991-10-01), Yasuda et al.
patent: 5349545 (1994-09-01), Keith

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