Registers – Transfer mechanism – Traveling pawl
Patent
1975-06-17
1977-01-04
Dildine, Jr., R. Stephen
Registers
Transfer mechanism
Traveling pawl
G06F 7385
Patent
active
040015700
ABSTRACT:
A digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format. Such adding and subtracting is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers. The two multidigit zoned decimal numbers to be added or subtracted at any given moment are supplied to the two input sides of such binary adder by way of input modifier circuits which precondition the zone and sign fields in such numbers to enable the proper propagation of digit carries across such zone and sign fields during the performance of the addition inside the binary adder. The resulting binary bit sequence appearing at the output side of the binary adder is passed to an output modifier or corrector which causes the bits in the zone and sign field positions therein to assume the proper zone and sign code values. The input modifier circuitry for one of the numbers also includes circuitry for increasing the value of each digit in such number by a factor of six for enabling the proper generation of digit carries inside the binary adder. The output corrector includes circuitry for reducing, when necessary, the value of one or more of the output digits by a factor of six to offset the increase in the input digits. Subtraction is accomplished by complementing one of the numbers before it is supplied to the binary adder. Sign handling circuitry detects the polarities or signs of the two input numbers as well as the status of an external add/subtract command and processes these three factors to develop a control signal for controlling the use of the complementing action for enabling the number appearing at the output of the output corrector to be in true magnitude form whenever possible. The input modifier circuitry, the output corrector and the sign handling circuitry are constructed so that packed binary coded decimal numbers and pure binary numbers can also be handled by the arithmetic unit.
REFERENCES:
patent: 3508037 (1970-04-01), Collins et al.
patent: 3752394 (1973-08-01), Igel
IBM Field Engineering Manual of Instruction--System/360 Model 50--Comprehensive Introduction, IBM Pub. No. SY22-2821-0, 4th ed., 1966, pp. 38-49.
IBM Field Engineering Theory of Operation--System/360 Model 50--Functional Units, IBM Pub. No. SY22-2822-1, 5th ed., 1965, pp. 35-41.
IBM Field Engineering Theory of Operation--System/360 Model 50-RS, SI, SS Instructions, IBM Pub. No. SY22-2825-1, 6th ed., 1966, pp. 55-58 and 68-74.
Franklin, J. W. Zoned or Packed Decimal Operand Detector, IBM Tech. Disc. Bull. 15(7): Dec. 1972, pp. 2097-2098.
Gooding David N.
Shimp Everett M.
Bee Richard E.
Dildine, Jr. R. Stephen
International Business Machines - Corporation
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