Arithmetic unit

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36473602, G06F 9302

Patent

active

058597891

ABSTRACT:
There is disclosed an arithmetic unit which allows a combined multiply-add operation to be carried out in response to execution of a single computer instruction. This is particularly useful in a packed arithmetic environment, when a operand comprises a plurality of packed objects and the intention is to carry out the same arithmetic operation on respective pairs of objects in different operands. There is also provided a computer and a method of operating a computer to effect the combined multiply-add operation.

REFERENCES:
patent: 4617625 (1986-10-01), Nagashima
patent: 4761754 (1988-08-01), Kinoshita
patent: 4771379 (1988-09-01), Hideki et al.
patent: 4888682 (1989-12-01), Ngai
patent: 5081573 (1992-01-01), Hall
patent: 5446651 (1995-08-01), Moyse
Standard Search Report issued by the European Patent Office and dated Feb. 13, 1996.
Proceedings Of the 7th IEEE Symposium on Computer Arithmetic, 4-6 Jun. 1985, Urbana, IL, USA, 1985 IEEE Computer Society Press, Los Alamitos CA US, pp. 38-43.
Electronic Design, vol. 32, No. 10, May 1984 Hasbrouck Heights, New Jersey US, pp. 191-206, W. Meshach "Data-Flow IC Makes Short Work Of Tough Processing Chores".

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