Arithmetic synthesizer frequency generation with reduced phase j

Details Arithmetic synthesizer frequency generation with reduced phase j Arithmetic synthesizer frequency generation with reduced phase j

1977-07-25

1979-03-13

Ruggiero, Joseph F.

Boots, shoes, and leggings

307227, 328 14, 328186, G06J 100, G06F 1534, H03K 402

Patent

active

041445791

ABSTRACT:
Arithmetic synthesizer having an output circuit that provides a linear phase output signal. A ramp generator controlled by the stepped output signal from the arithmetic synthesizer interpolates the value of the signal slope between steps to supply a phase output having low noise, i.e., reduced time jitter.

REFERENCES:
patent: 3654450 (1972-04-01), Webb
patent: 3676784 (1972-07-01), Le Comte
patent: 3689914 (1971-08-01), Butler
patent: 3918046 (1975-11-01), Rivers
patent: 3973209 (1976-08-01), Nossen et al.
patent: 4021757 (1977-05-01), Nossen
Gehweiler et al.--"CMOS/SOS Developments for Signal Processing Applications"--Ninth Annual Asilomar Conference--Nov. 1975.

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