Arithmetic processor using signed digit representation of intern

Details Arithmetic processor using signed digit representation of intern Arithmetic processor using signed digit representation of intern

1990-10-16

1992-10-06

Malzahn, David H.

Boots, shoes, and leggings

G06F 749

Patent

active

051538474

ABSTRACT:
This invention discloses an arithmetic processor which represents internal arithmetic operands as signed-digit numbers, each digit of which may have either positive, zero, or negative values and which executes addition of a plurality of numbers each of whose most significant digit is offset with respect to the other numbers. The arithmetic processor includes an adder tree which is so constituted that a pair of said plurality of numbers are added to obtain a partial sum and further pairs of partial sums are successively added to obtain a final sum of all numbers. The arithmetic processor further comprises first means for adding a portion of the two numbers where both digits are present, second means for causing a lower order portion where only one of the numbers has a digit present to directly become part of the sum, third means for retaining or outputting a carry created by the first means, and fourth means for adding the carry created in each add stage of the adder tree to the later add stages of the adder tree to obtain the sum.

REFERENCES:
patent: 4230908 (1980-10-01), Davis et al.
patent: 4590584 (1986-05-01), Yaguchi et al.
patent: 4628472 (1986-12-01), Fensch
patent: 4638449 (1987-01-01), Frey
patent: 4791601 (1988-12-01), Tanaka
patent: 4864528 (1989-09-01), Nishiyama et al.
patent: 4871270 (1989-03-01), Nash
Avizienis, "Binary-Compatible Signed-Digit Arithmetic" Proceedings--Fall Joint Computer Conf., 1964 pp. 663-672.
Hwang, Computer Arithmetic, Principles, Architecture and Design John Wiley & Sons 1979 pp. 149-151.
A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation, Takagi, et al., IECE Japan, vol. 167, D #4 pp. 450-457.
A VLSI-Oriented High-Speed Multiplier Using Redundant Binary Adder Tree, Takagi, et al., IECE Japan, vol. J66.d, pp. 683-690.
A New Class of Digital Division Methods, James Robertson, IRE Transactions on Electronic Computers, pp. 218-222.
Signed-Digit Number Representations for Fast Parallel Arithmetic, Avizienis, IRE Transactions on Electronic Computers pp. 389-400.
A Class of Binary Divisions Yielding Minimally Represented Quotients Metze IRE Transactions on Electronic Computers, pp. 761-764.
Design of the Arithmetic Units of ILLIAC III, Redundancy & Higher Radix Methods, Atkins, IEEE Transacts. on Computers vol. C-19, pp. 720-732.
Multiple Operand Addition and Multiplication, Shanker Singh et al. IEEE Transactions on Computers, vol. C-22, No. 2 pp. 113-120.
Concise Papers, Lyon, IEEE Transactions on Communications, pp. 418-425.
Real-Time Processing Gains Ground with Fast Digital Multiplier, Waser, et al. Electronics, pp. 93-99.
High Speed Multiplier Using A Redundant Binary Adder tree, Harata, et al. IEEE International Conference on Computer Design, pp. 165-170, 1984.
High Speed VLSI Multiplication Algorithm With A Redundant Binary Array Addition Tree, Takagi, et al. IEEE Transactions on Computers, vol. C-34, No. 9, pp. 1789-1795.
Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation, Kuninobu, et al., Proceedings 8th Symposium on Computer Arithmetic, pp. 80-86.

Affiliated with

Also associated with

Rating

Arithmetic processor using signed digit representation of intern does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Arithmetic processor using signed digit representation of intern, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arithmetic processor using signed digit representation of intern will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1195690