Arithmetic processor using redundant signed digit arithmetic

Details Arithmetic processor using redundant signed digit arithmetic Arithmetic processor using redundant signed digit arithmetic

1987-06-25

1989-10-10

Malzahn, David H.

Boots, shoes, and leggings

364761, G06F 749

Patent

active

048736600

ABSTRACT:
A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operation from an internal operand such as augend (or minuend) and an addend (or subtrahend) for each digit in addition (or subtraction) of signed digit numbers, carried out as an internal arithmetic operation, and determines an intermediate sum (or intermediate difference). In a second step arithmetic operation, the processor obtains a final sum (or difference) for each digit from the intermediate sum (or intermediate difference) obtained in the first step arithmetic operation and an intermediate carry (or intermediate borrow) from a lower order arithmetic operation. The sign of an internal operand is either inverted or the internal operand is converted to 0 in accordance with the value of a control signal and then provided as the internal operand for processing in the first step arithmetic operation. Such sign inversion or conversion of the operand to zero enables the first and second step arithmetic operations to be performed utilizing addition and/or subtraction only.

REFERENCES:
Avizienis, "Binary-Compatible Signed-Digit Arithmetic" Proceedings-Fall Joint Computer Conference, 1964, pp. 663-672.
Tung "Division Algorithm for Signed-Digit Arithmetic" IEEE Trans. on Computers, Sep. 1968, pp. 887-889.
Atkins, "Design of the Arithmetic Units of Illiac III: Use of Redundancy & Higher Radix Methods" IEEE Trans. on Computers, vol. c-19 No. 8, Aug. 1970, pp. 720-733.
A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation, Takagi, et al, IECE Japan, vol. 167 D #4, pp. 450-457 4/84.
A VLSI-Oriented High-Speed Multiplier Using Redundant Binary Adder Tree, Takagi, et al. IECE Japan, vol. J66.d, pp. 683-690 6/84.
A New Class of Digital Division Methods, James Robertson, IRE Transactions on Electronic Computers, pp. 218-222, 9/58.
Signed-Digit Representations for Fast Parallel Arithmetic, Avizienis, IRE Transactions on Electronic Computers, pp. 389-400, 9/61.
A Class of Binary Divisions Yielding Minimally Represented Quotients Metze IRE Transactions on Electronic Computers, pp. 761-764 12/62.
Multiple Operand Addition and Multiplication, Shanker Singh et al. IEEE Transactions on Computers, vol. C-22, No. 2 pp. 113-120, 2/73.
Concise Papers, Lyon, IEEE Transactions on Communications, pp. 418-425, 4/76.
Real-Time Processing Gains Ground with Fast Digital Multiplier, Waser, et al. Electronics, pp. 93-99, 9/77.
High Speed Multiplier Using a Redundant Binary Adder Tree, Harata, et al. IEEE International Conference on Computer Design, pp. 165-170, 1984.
High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree, Takagi, et al. IEEE Transactions on Computers, vol. C-34, No. 9, pp. 1789-1795, 9/85.
Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation, Kuninobu, et al., Proceedings 8th Symposium on Computer Arithmetic, pp. 80-86, 5/87.

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