Arithmetic processor performing mask and trap operations for exc

Details Arithmetic processor performing mask and trap operations for exc Arithmetic processor performing mask and trap operations for exc

1988-11-16

1990-10-02

Harkcom, Gary V.

Boots, shoes, and leggings

G06F 700

Patent

active

049611615

ABSTRACT:
A floating-point arithmetic processor performs a MASK or TRAP operation in response to occurrence of an exception. This processor includes a first flag which is set when the exception occurs, a second flag storing first data designating the MASK operation or second data designating the TRAP operation. A third flag is set when the first flag is set and the second flag is storing the second data. A controller produces a default value in response to the occurrence of the exception. The processor also includes a destination register, which is accessible by a central processing unit (CPU), and a transfer gate circuit which takes an open state to allow the default value to be stored into the destination register when the third flag is not set and a closed state to inhibit the default value to be stored into the destination register when the third flag is set.

REFERENCES:
patent: 4460970 (1984-07-01), McClary
patent: 4777593 (1988-10-01), Yoshida
ANSI/IEEE Std 754-1985, "IEEE Standard for Binary Floating-Point Arithmetic", IEEE, 1985, pp. 7-18.

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