Arithmetic processor and multiplier using redundant signed digit

Boots – shoes – and leggings

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

364760, G06F 749, G06F 752

Patent

active

048645281

ABSTRACT:
A high speed processor including a multiplier is disclosed. The multiplier includes a multiplier recorder circuit which may record multipliers in groups of digits, and intermediate partial product generators which generate partial products from the recorded digits and a multiplicand. Addition/subtraction is then carried out on the intermediate partial products generated by the partial product generators. The processor may operate using signed digit expressions.

REFERENCES:
patent: 4745570 (1988-05-01), Diedrich et al.
A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation, Takagi et al, IECE, Japan, vol. 67, D. #4, pp. 450-457, 4/84.
A VLSI-Oriented High-Speed Multiplier Using Redundant Binary Adder Tree, Takagi et al., IECE, Japan, vol. J66.d, pp. 683-690, 6/84.
A New Class of Digital Division Methods, James Robertson, IRE Transactions on Electronic Computers, pp. 218-222, 9/58.
Signed-Digit Number Representations for Fast Parallel Arithmetic, Avizienis, IRE Transactions on Electronic Computers, pp. 389-400, 9/61.
A Class of Binary Divisions Yielding Minimally Represented Quotients, Metze, IRE Transactions on Electronic Computers, pp. 761-764, 12/62.
Design of the Arithmetic Units of ILLIAC III, Redundancy & Higher Radix Methods, Atkins, IEEE Transacts. on Computers, vol. C-19, pp. 720-732, 8/70.
Multiple Operand Addition and Multiplication, Shanker Singh et al., IEEE Transactions on Computers, vol. C-22, pp. 113-120, 2/73.
Concise Papers, Lyon, IEEE Transactions on Communications, pp. 418-425, 4/76.
Real-Time Processing Gains Ground with Fast Digital Multiplier, Waser et al., Electronics, pp. 93-99, 9/77.
High Speed Multiplier Using a Redundant Binary Adder Tree, Harata et al., IEEE International Conference on Computer Design, pp. 165-170, 1984.
High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree, Takagi et al., IEEE Transactions on Computers, vol. C-34, No. 9, pp. 1789-1795, 9/85.
Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation, Kuninobu et al., Proceedings 8th Symposium on Computer Arithmetic, pp. 80-86, 5/87.
Avizienis, "Binary-Compatible Signed-Digit Arithmetic", Proceedings-Fall Joint Computer Conference, 1964, pp. 663-672.
Tung, "Division Algorithm for Signed-Digit Arithmetic", IEEE Trans. on Computers, Sep. 1968, pp. 887-889.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Arithmetic processor and multiplier using redundant signed digit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Arithmetic processor and multiplier using redundant signed digit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arithmetic processor and multiplier using redundant signed digit will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-249317

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.