Boots – shoes – and leggings
Patent
1987-07-07
1989-10-31
Malzahn, David H.
Boots, shoes, and leggings
364761, G06F 749
Patent
active
048781924
ABSTRACT:
An arithmetic processor and an addition/subtraction circuit therefor are disclosed. The arithmetic processor comprises a plurality of the addition/subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) with respect to respective digits of two operands. An addition/subtraction unit comprises a first circuit and a second circuit coupled to receive binary signals each representing a respective digit of the operands. At least a first of the two binary signals is a 2-bit signal representing a signed digit expression, one bit of which ("the sign bit") represents the sign of one of the digits of the operands and the other bit of which ("the magnitude bit") represents the magnitude of that one digit of the operands. The first circuit provides a binary signal representing an intermediate carry (or borrow) and the second circuit provides a binary signal representing an intermediate sum (or difference) from the two binary signals representing the digits of the operands. The addition/subtraction unit further comprises a third circuit which is coupled to receive the intermediate sum (or difference) binary signal output from the second circuit and a binary signal representing an intermediate carry (or borrow) from a next-lower-order digit, and outputs a 2-bit binary signal representing an addend (or subtrahend). That 2-bit signal output by the third circuit represents a signed digit expression, one bit, i.e., the sign bit, represents the sign of the addend (or subtrahend) and the other bit, i.e., the magnitude bit, represents the magnitude of the addend (or subtrahend).
REFERENCES:
Avizienis, "Binary-Compatible Signed-Digit Arithmetic", Proceedings-Fall Joint Computer Conference, 1964, pp. 663-672.
Tung, "Division Algorithm for Signed-Digit Arithmetic", IEEE Trans. on Computers, Sep. 1968, pp. 887-889.
Atkins, "Design of the Arithmetic Units of ILLIAC III: Use of Redundancy & Higher Radix Methods", IEEE Trans. on Computers, vol. C-19, No. 8, Aug. 1977, pp. 720-733.
A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation, Takagi et al., IECE Japan, vol. 167.D, #4, pp. 450-457, 4/84.
A VLSI-Oriented High-Speed Multiplier Using Redundant Binary Adder Tree, Takagi et al., IECE Japan, vol. J66.d, pp. 683-690, 6/84.
A New Class of Digital Division Methods, James Robertson, IRE Transactions on Electronic Computers, pp. 218-222, 9/58.
Signed-Digit Number Representations for Fast Parallel Arithmetic, Avizienis, IRE Transactions on Electronic Computers, pp. 389-400, 9/61.
A Class of Binary Divisions Yielding Minimally Represented Quotients, Metze, IRE Transactions of Electronic Computers, pp. 761-764, 12/62.
Design of the Arithmetic Units of ILLIAC III, Redundancy & Higher Radix Methods, Atkins, IEEE Transacts. on Computers, vol. C-19, pp. 720-732, 8/70.
Multiple OPerand Addition and Multiplication, Shanker Singh et al., IEEE Transactions on Computers, vol. C-22, No. 2, pp. 113-120, 2/73.
Concise Papers, Lyon, IEEE Transactions on Communications, pp. 418-425, 4/76.
Real-Time Processing Gains Ground with Fast Digital Multiplier, Waser et al., Electronics, pp. 93-99, 9/77.
High Speed Multiplier Using A Redundant Binary Adder Tree, Harata et al., IEEE International Conference on Computer Design, pp. 165-170, 1984.
High Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree, Takagi et al., IEEE Transactions on Computers, vol. C-34, No. 9, pp. 1789-1795, 9/85.
Design of High Speed MOS Multiplier and Divider Using Redundant Binary Representation, Kuninobu et al., Proceedings 8th Symposium on Computer Arithmetic, pp. 80-86, 5/87.
Kuninobu Shigeo
Nishiyama Tamotsu
Malzahn David H.
Matsushita Electric - Industrial Co., Ltd.
LandOfFree
Arithmetic processor and divider using redundant signed digit ar does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arithmetic processor and divider using redundant signed digit ar, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arithmetic processor and divider using redundant signed digit ar will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-630292