Arithmetic processor and arithmetic method

Details Arithmetic processor and arithmetic method Arithmetic processor and arithmetic method

1994-04-26

1997-06-03

Ngo, Chuong D.

Boots, shoes, and leggings

G06F 752

Patent

active

056361556

ABSTRACT:
An arithmetic processor employs two modes of nonpipeline operation and pipeline operation, and is provided with a redundant binary multiplication part for generating redundant binary multiplied results and a supplementary term, first to third intermediate latches for storing two pairs of partial product added results and the supplementary term, a redundant binary accumulation part for accumulating the results of first to third intermediate latches and a value of an accumulation result latch to store the thus accumulated result into the accumulation result latch, and a redundant binary/binary conversion part for converting into a binary numeral the result of the redundant binary multiplication part or the result of the redundant binary accumulation part. Thereby high-speed operations of multiplication instruction and product-sum operation instruction are achieved.

REFERENCES:
patent: 4727507 (1988-02-01), Miyanaga
patent: 4769780 (1988-09-01), Chang
patent: 4864528 (1989-09-01), Nishiyama et al.
patent: 5220525 (1993-06-01), Anderson et al.
patent: 5231415 (1993-07-01), Hagihara
patent: 5253195 (1993-10-01), Broker et al.

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