Arithmetic processing method and apparatus for performing arithm

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G06F 738

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active

049338935

ABSTRACT:
An arithmetic processing method and apparatus having first and second input registers and an arithmetic unit having a plurality of stages wherein an intermediate operation result of a previous iterative operation and input data are used to perform further iterative operations and obtain a final operation result as a vector sum. A serial number of input data is identified to check the order of the imputted data among a series of data to be processed. A control pattern to be used for control of the stages of the arithmetic processing unit is selected based on the identified serial number. The operation to be performed at each stage of the arithmetic processing unit is controlled in accordance with the selected control pattern, to obtain a final operation result to be outputted within a minimum number of operation cycles.

REFERENCES:
patent: 4757444 (1988-07-01), Aoyama et al.
patent: 4823258 (1989-04-01), Yamazaki

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