Arithmetic processing apparatus

Details Arithmetic processing apparatus Arithmetic processing apparatus

1997-06-05

1998-09-15

Sheikh, Ayaz R.

Boots, shoes, and leggings

36476002, G06F 750, G06F 752

Patent

active

058089284

ABSTRACT:
A partial product adder for summing up four partial products P0, P1, P2, and P3 which are binary numbers in twos-complement representation having different weights is composed of a carry save adder consisting of an array of 4:2 compressors each having four inputs. Of the four inputs of each 4:2 compressor, the input W presents the shortest propagation delay, while the inputs Y and Z compose critical paths. To implement sign extension of the first partial product P0 having the smallest weight, a logic circuit provides, in a plurality of digit positions higher than the sign digit P0s of the first partial product, values resulting from a logic operation between the value of the sign digit P0s of the first partial product and the value of the sign digit P1s of the second partial product having the second smallest weight. The first partial product P0 after sign extension is allocated to the input W of the carry save adder, while the plurality of upper digits of the input Z related to the second partial product P1 have their values fixed to 0. This reduces a time penalty accompanying the sign extension.

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M.R. Santoro et al., "SPIM: A Pipelined 64.times.64-bit Iterative Multiplier", IEEE Journal of Solid-State Circuits, vol. 24, No. 2, pp. 487-493, Apr. 1989.

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