Electrical computers: arithmetic processing and calculating – Electrical digital calculating computer – Particular function performed
Patent
1996-04-10
1999-11-02
Malzahn, David H.
Electrical computers: arithmetic processing and calculating
Electrical digital calculating computer
Particular function performed
708626, 708210, G06F 750
Patent
active
059788275
ABSTRACT:
In a processor for performing operations including an addition of a plurality of multiple bit data, values on common places of a plurality of multiple bit data are entered in parallel into number detectors set for respective places, the number of the high signals in the input values is output in the binary notation, and outputs from a plurality of NDs are added by full adders to execute a high speed operation without carries. In addition, values with no common places are integrated into single data before being added.
REFERENCES:
patent: 3524977 (1970-08-01), Wang
patent: 3535502 (1970-10-01), Clapper
patent: 3603776 (1971-09-01), Weinberger
patent: 3636334 (1972-01-01), Svoboda
patent: 3675001 (1972-07-01), Singh
patent: 3723715 (1973-03-01), Chen et al.
patent: 3795880 (1974-03-01), Singh et al.
patent: 3950636 (1976-04-01), Dao
patent: 4839850 (1989-06-01), Noll et al.
patent: 5095457 (1992-03-01), Jeony
Alta Frequenza, vol. 45, No. 10, Oct. 1976, Milano IT, pp. 349-356, XP002007107, L. Dadda: "Some Schemes for Parallel Multipliers".
IEEE Transactions on Computers, vol. 26, No. 10, 1977, New York US, pp. 948-957, XP002007108, W. Stenzel, et al., "A Compact High-Speed Parallel Multiplication Scheme".
IBM Technical Disclosure Bulletin, vol. 24, No. 3, Aug. 1981, New York US, pp. 1713-1716, XP002007109, R. Hitchcock, Sr.: "Fast Multiply Circuit".
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, Jun. 4-6, 1985, IEEE Computer Society Press, Loss Alamitos CA US, pp. 16-19, XP002007110, H. Kobayashi: "A Multioperand Two's Complement Addition Algorithm".
Rubinfield, L., IEEE Trans. on Computers, C24, 10, 1975, pp. 1014-1015, "Proof of the Modified Booth's Algorithm for Multiplication".
Hanyu et al. Proc. IEEE Int. Symp. on MVL, May 1994, pp. 19-26, "Multiple-Valued Current-Mode MOS Integrated Circuits Based on Dual-Rail Source-Coupled Logic".
Wallace, C., IEEE Trans. on Elec. Computers, EC-13, 1, 1964, pp. 14-17, "A Suggestion for a Fast Multiplier".
Canon Kabushiki Kaisha
Malzahn David H.
LandOfFree
Arithmetic processing does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Arithmetic processing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Arithmetic processing will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2150081