Arithmetic operation unit and memory accessing device for access

Details Arithmetic operation unit and memory accessing device for access Arithmetic operation unit and memory accessing device for access

1992-11-19

1996-08-27

Gossage, Glenn

Boots, shoes, and leggings

395287, 395294, 395308, 395449, 395467, 395478, 395403, 395800, 3642318, 36424291, 36424292, 36424341, 36493541, 36493546, 36494834, 3649613, 36496426, 36496432, 364DIG1, 364DIG2, 36493151, 36423221, G06F 1336, G06F 1300, G06F 15347, G06F 1200

Patent

active

055510108

ABSTRACT:
A memory accessing device is coupled to a first bus which connects a first buffer storage unit in a central processing unit to a second buffer storage unit. The memory accessing device can access, through the first bus, at least one of the first buffer storage unit and the second buffer storage unit independently of the central processing unit. The memory accessing device includes an address generating circuit for generating an address to access either or both of the first buffer storage unit and the second buffer storage unit. An output control unit in the memory accessing device outputs the address generated by the address generating circuit to the first bus. An output of the control unit enter an idle state if the second buffer storage unit issues a request for access to the first buffer storage unit when the memory accessing device obtains a right to use the first bus.

REFERENCES:
patent: 4594682 (1986-06-01), Drimak
patent: 4665483 (1987-05-01), Ciacci et al.
patent: 4888679 (1989-12-01), Fossum et al.
patent: 5056011 (1991-10-01), Yashitake et al.
patent: 5276818 (1994-01-01), Okazawa et al.

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