Arithmetic operation system for binary addition/subtraction

Details Arithmetic operation system for binary addition/subtraction Arithmetic operation system for binary addition/subtraction

1997-09-11

1999-08-31

Mai, Tan V.

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

708671, 3401462, G06F 700, G06F 750

Patent

active

059447710

ABSTRACT:
In an arithmetic operation circuit, a coincidence detector receives the sign bits of binary data so as to output a truth coincidence detection signal when the two sign bits coincide with each other, and to output a false coincidence detection signal when they do not coincide with each other. A data inverter outputs a logic-inverted signal of each bit of the data when the coincidence detection result is truth, and outputs a signal equal to the data when the coincidence detection result is false. An adder receives the coincidence detection signal as a carry signal, and outputs the sum of the data and the output from the data inverter. A flag generator receives the sign bit of the data and the sign bit of the sum from the adder, and selectively outputs the sign bit or its inverted bit.

REFERENCES:
patent: 5373459 (1994-12-01), Taniguchi
patent: 5563813 (1996-10-01), Chen et al.
patent: 5793655 (1998-08-01), Harlap et al.

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