Arithmetic operation circuit

Details Arithmetic operation circuit Arithmetic operation circuit

1981-07-23

1984-04-03

Smith, Jerry

Boots, shoes, and leggings

364757, 364764, 364786, 364787, G06F 752, G05F 750

Patent

active

044411588

ABSTRACT:
There is disclosed an arithmetic operation circuit including an adder for performing a multiplication and a division. A one stage arithmetic cell group is formed by connecting eight arithmetic cells. Eight stage arithmetic cell groups are set in the obliquely shifted arrangement and a ninth arithmetic cell group is provided corresponding to the shifts of their arithmetic cell groups in the array. A partial carry circuit is connected to the respective arithmetic cell groups. The arithmetic cells are all comprised of complementary MOS gates and the carry circuit is comprised of enhancement/depletion type MOS gates.

REFERENCES:
patent: 3535498 (1970-10-01), Smith, Jr.
patent: 3535502 (1970-10-01), Clapper
patent: 4153938 (1979-05-01), Ghest et al.
patent: 4168530 (1979-09-01), Gajski et al.
Agrawal, High-Speed Arithmetic Arrays, IEEE Transaction on Computers 215, vol. c-28, No. 3 (Mar. 1979).

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