Arithmetic operation circuit

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364784, 307472, G06F 750

Patent

active

049071840

ABSTRACT:
An arithmetic operation circuit is provided which includes a logic processing circuit having a first metal-oxide-semiconductor-field-effect-transistor (MOSFET) column cascade-connecting a plurality of MOSFETs and a second MOSFET column cascade-connecting a plurality of MOSFETs. First and second ends of the second MOSFET column are respectively connected to first and second ends of said first column. A first power supply voltage is coupled to the common connecting point of the first ends of said first and second MOSFET columns. An amplifying circuit, including the grounded emitter type bipolar transistor, is provided such that the base thereof is connected to the common connecting point of the second ends of said first and second MOSFET columns.

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Hotta et al., "CMOS/Bipolar Circuits for 60-MHZ Digital Processing", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 802-812.

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