Arithmetic operating device for digital signal processing and me

Details Arithmetic operating device for digital signal processing and me Arithmetic operating device for digital signal processing and me

1997-08-15

1999-08-10

Malzahn, David H.

Boots, shoes, and leggings

G06F 738

Patent

active

059368705

ABSTRACT:
An arithmetic operating device and method for a digital signal processing (DSP) having a fixed bit number of input/output data bits significantly decreases the time conventionally spent on buffering in a converter. The device includes a sign bit extender for increasing number of sign bits an input data DATA.sub.-- IN, an adder for adding up the input data DATA.sub.-- IN which passed through the sign bit extender and a feedback data DATA.sub.-- ACC, an accumulator for accumulating a present output data and a previous output data from the adder, an overflow detector for detecting an overflow of the data DATA.sub.-- ACC outputted from the accumulator in accordance with an extended sign bit therein, and a saturation logic unit for converting the number of sign bits in the data DATA.sub.-- ACC outputted from the accumulator to an initial number of sign bits in the input data DATA.sub.-- IN in accordance with a signal OF outputted from the overflow detector, wherein the accumulator outputs the data DATA.sub.-- ACC to the adder while an arithmetic operation is proceeding therein, and the accumulator outputs the data DATA.sub.-- ACC to the overflow detector and to the saturation logic unit when the entire arithmetic operation is completed.

REFERENCES:
patent: 4379338 (1983-04-01), Nishitani et al.
patent: 5251166 (1993-10-01), Ishida

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