Arithmetic logic unit with zero-result prediction

Details Arithmetic logic unit with zero-result prediction Arithmetic logic unit with zero-result prediction

1996-05-24

1997-02-18

Mai, Tan V.

Boots, shoes, and leggings

36471509, 3647365, G06F 700

Patent

active

056046898

ABSTRACT:
An arithmetic logic unit provides for zero-result prediction so as to eliminate the latency between successive operations (e.g., multiplication and division) when a zero detection is a condition for performance of the second operation. Instead of performing zero detection on the result, zero prediction is performed on the initial or intermediate operands, (e.g., partial products that are summed to generate a product). To this end, zero-prediction logic determines whether or not both of the following conditions are met: 1) either the least significant bits of the addends are the same and the carry-in is zero or the least significant bits of the addends are different and the carry-in is one. 2) for each pair of adjacent bit positions, the four included bits are consistent with addend complementarity. If both conditions are met, a zero result is predicted; otherwise, a non-zero result is predicted.

REFERENCES:
patent: 3983382 (1976-09-01), Weinberger
patent: 4630192 (1986-12-01), Wassel et al.
patent: 4924422 (1990-05-01), Vassiliadis et al.
patent: 5091874 (1992-02-01), Watanabe et al.
patent: 5367477 (1994-11-01), Hinds et al.

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