Arithmetic logic unit with improved critical path performance

Details Arithmetic logic unit with improved critical path performance Arithmetic logic unit with improved critical path performance

1996-07-22

1998-06-09

Malzahn, David H.

Boots, shoes, and leggings

364788, G06F 750

Patent

active

057645507

ABSTRACT:
An arithmetic logic unit (ALU) with improved critical path performance includes two sets of adder circuits, a logic circuit, a set of multiplexors and a decoder. The adder circuits perform redundant add operations, one with a unit carry input and one without a carry input, upon multiple respective portions of the two sets of input signal bits. The logic circuit performs Boolean logic operations upon the two sets of input signal bits. In accordance with a set of selection control signals, the multiplexors select among the multiple results of such redundant add operations and Boolean logical operations for outputting as the final output bits. Such selection control signals are generated by the decoder based upon the contents of the two sets of input signal bits.

REFERENCES:
patent: 3100835 (1963-08-01), Bedrij
patent: 4573137 (1986-02-01), Ohhashi
patent: 4682303 (1987-07-01), Uya
patent: 5272662 (1993-12-01), Scriber et al.
patent: 5285406 (1994-02-01), Lynch et al.
patent: 5299319 (1994-03-01), Vassiliadis et al.
Neil H.E. Weste and Kamran Eshraghian, "Principles of VMOS VLSI Design", A Systems Perspective, 1985, pp. 331-333.

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