Boots – shoes – and leggings
Patent
1993-11-30
1998-09-08
Shah, Alpesh M.
Boots, shoes, and leggings
395100, 364736, 3642328, 364258, 364260, 364DIG1, G06F 1300
Patent
active
058059130
ABSTRACT:
A data processing apparatus having an arithmetic logic unit (230) with conditional register source selection includes a plurality of data registers (200), a status register (210) storing at least one status bit, an arithmetic logic unit (230) and an instruction decode logic (245, 246, 250). The instruction decode logic (245, 246, 250) responds to a received register pair conditional source instruction to supply data from either a first register or a second register to the first input of said arithmetic logic unit (230) depending on the digital state of a status bit. Preferably an instruction field indicates whether the instruction involves conditional register pair source selection. There are preferably a plurality of status bits and the register pair conditional source instruction determines which status bit controls the source selection. A prior output of the arithmetic logic unit (230) sets the plural status bits. These may include negative, carry, overflow and zero. The instruction word may designate one or more of these status bits not changed by the current instruction. The data registers (200) are preferably accessed via consecutive register numbers, the first register having an odd register number and the second register having an even register number one less.
REFERENCES:
patent: 4023023 (1977-05-01), Bourrez et al.
patent: 4037094 (1977-07-01), Vandierendonck
patent: 4041461 (1977-08-01), Kratz et al.
patent: 4179746 (1979-12-01), Tubbs
patent: 4296469 (1981-10-01), Gunter et al.
patent: 4325121 (1982-04-01), Gunter et al.
patent: 4338661 (1982-07-01), Tredennick
patent: 4546428 (1985-10-01), Morton
patent: 4580215 (1986-04-01), Morton
patent: 4821225 (1989-04-01), Ando et al.
patent: 4872131 (1989-10-01), Kubota et al.
patent: 5109495 (1992-04-01), Fite et al.
patent: 5148547 (1992-09-01), Kahle et al.
patent: 5197140 (1993-03-01), Balmer
patent: 5212777 (1993-05-01), Gove et al.
patent: 5226125 (1993-07-01), Balmer et al.
patent: 5239654 (1993-08-01), Ing-Simmons et al.
patent: 5345410 (1994-09-01), Yokohama et al.
Henle et al, "Desktop Computers, in Perspective", 1992, pp. 3, 4, 8, 13, 602-604.
Motorola, "MC68030", 1989.
Microcontroller Report, Slater, Michael, "IIT Ships Programmable Video Processor," vol. 5, No. 20, Oct. 30, 1991, pp. 1, 6-7, 13.
Balmer Keith
Guttag Karl M.
Donaldson Richard L.
Kesterson James C.
Marshall, Jr. Robert D.
Shah Alpesh M.
Texas Instruments Incorporated
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