Arithmetic logic unit over finite field GF(2 m )

Details Arithmetic logic unit over finite field GF(2 m ) Arithmetic logic unit over finite field GF(2 m )

2007-08-21

2007-08-21

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

10771592

ABSTRACT:
Disclosed herein is an arithmetic logic unit over a finite field GF(2m). Arithmetic logic units consistent with the present invention are disclosed as implemented using a division algorithm based on a binary greatest common divisor algorithm and a Most Significant Bit-first multiplication algorithm. The arithmetic logic unit can perform both a multiplication and a division using shared logic. Since the arithmetic logic unit has no limitations in the selection of an irreducible polynomial, and it is very regular and easily formed as a module, the arithmetic logic unit of the present invention has high expansibility and flexibility with respect to the size m of a field. Further, since the arithmetic logic unit of the present invention can perform a multiplication and a division using shared logic, it is very suitable to implement an encryption system for application products requiring a small size, such as smart cards or wireless communication devices.

REFERENCES:
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patent: 6795553 (2004-09-01), Kobayashi et al.
patent: 6836784 (2004-12-01), Perkins
patent: 7068785 (2006-06-01), Perkins

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