Arithmetic logic unit for floating point data and/or fixed point

Details Arithmetic logic unit for floating point data and/or fixed point Arithmetic logic unit for floating point data and/or fixed point

1985-02-12

1986-10-28

Malzahn, David H.

Boots, shoes, and leggings

235310, G06F 750, H03M 724

Patent

active

046202927

ABSTRACT:
A signal processor having a wide dynamic range and which can process both data in the fixed point representation and data in the floating point representation by the use of a single floating-point arithmetic circuit is capable of processing digital signals, such as voice signals, at high speed and in real time. In addition, this signal processor includes an arithmetic logic unit for floating point data and/or fixed point data in which there is selectively provided a first pair of first and second floating point data which are to be subjected to an arithmetic operation, or a second pair of data consisting of third floating (fixed) point data which is to be converted to fixed (floating) point data and fourth floating point data which is a reference data for the conversion. If the first pair is selected the first and second pair of floating point data are subjected to the arithmetic operation. If the second pair is selected, the conversion of the fixed (floating) point data to floating (fixed) point data is effected by normalizing the third data with the value of the exponent part of the fourth data.

REFERENCES:
patent: 3551665 (1970-12-01), Powers et al.
patent: 3697734 (1972-10-01), Booth et al.
patent: 3829673 (1974-08-01), Bouton, Jr. et al.
patent: 4476537 (1984-10-01), Blau et al.
Smith et al., "Fixed-Point, Floating-Point Adder", Technical Notes, A Publication of RCA, Princeton, NJ., TN No. 846, 3 sheets, Oct. 8, 1969.

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